TDA8046 Datasheet, PDF (9/48 Pages) NXP Semiconductors – Multi-mode QAM demodulator

Philips Semiconductors
Multi-mode QAM demodulator
Product specification
TDA8046
7.1 Functional description of the individual blocks
The functional block diagram of the multi-mode QAM
demodulator is illustrated in Fig.1. This section describes
the individual blocks in the demodulator. After adaptation
for the used input format (2’s complement or binary), the
input signal is demodulated in the I and Q baseband
signals which are applied to the inputs of the half-Nyquist
filter (equals square root raised cosine). To avoid
overloading of the ADC, an AGC detector is placed after
the adaptation for the input format. The control value for
the clock recovery is generated after half Nyquist filtering.
The echoes created in the cable network are reduced
significantly in the equalizer.
The equalizer produces a ‘clean’ constellation diagram
from which the information for the carrier recovery is
derived. This constellation is also applied to the output
formatter which demaps the transmitted symbols in
corresponding bits. The carrier recovery and lock
detection functions are based on the equalizer output.
The output of the equalizer is applied to an output
formatter, which translates the symbol bits to a FEC input
format. The digital outputs of the clock recovery, AGC, and
carrier recovery section are converted into currents which
are integrated by the loop filters.
To make these loop filters active, operational amplifiers
are integrated on the chip.
The TDA8046 can handle five different digital modulation
schemes; 4, 16, 32, 64 and 256-QAM. These schemes
are selectable via the I²C-bus interface.
7.1.1
QUADRATURE DEMODULATOR AND HALF NYQUIST
FILTER
Quadrature demodulation is accomplished after selection
of the appropriate input format via the I²C-bus.
The in-phase and quadrature components are both
applied to a half Nyquist filter. In default mode, this filter
gives a 20% roll-off half Nyquist shaping. The basic
schematic of the quadrature demodulator followed by the
half Nyquist filter is shown in Fig.4. The signs of the
multiplication factors in the Q-branch can be inverted
(I²C-bus bit INVD).
When using an 8-bit ADC the LSB of the 9-bit input word
should be connected to the positive supply (V_DDD).
This ensures a symmetrical 2’s complement
representation which can be multiplied by −1 in a correct
(2’s complement) way. The overall transfer function of the
square root raised cosine filters is shown in Figs 5 and 6.
For characteristics see Chapter 10.
handbook, full pagewidth
DIN8 ₉
to
DIN0
BINARY OR
TWO's
COMPLEMENT
I²C-BUS
I²C-BUS
9
I
+1, 0, −1, 0
0, −1, 0, +1
9
Q
HALF NYQUIST
FILTER
HALF NYQUIST
FILTER
I²C-BUS
I²C-BUS
MGG168
Fig.4 Schematic diagram of the quadrature demodulator and half Nyquist filter.
1996 Nov 19
9