TDA8046 Datasheet, PDF (17/48 Pages) NXP Semiconductors – Multi-mode QAM demodulator

Philips Semiconductors
Multi-mode QAM demodulator
Product specification
TDA8046
7.1.6 AGC
The AGC estimates the mean power based on the digital
input signal and relates this to a peak value for a given
constellation. To avoid overloading of the ADC, this
estimation of the peak signals is used to control the AGC
loop. The implemented AGC covers a range of ±20 dB in
gain variance. A schematic diagram of the AGC is
illustrated in Fig.13.
If the SAW filter does not have sufficient adjacent channel
attenuation, the AGC threshold can be varied to avoid
clipping of the ADC. To do this, the threshold is made
programmable via the I²C-bus (byte ATH). Table 2 shows
that for each mode, a new ATH value (on address 08)
must be set with the help of the I²C-bus.
The I²C-bus data on address 08 is a factor 16 smaller than
the used AGC threshold ATH.
The DAC output current range can be varied via the
I²C-bus interface (bits AGCA and AGCB) and the sign of
the current can be inverted (bit AGCI). The definition of the
DAC currents and the expected frequency behaviour of
the AGC is illustrated in Fig.14.
For characteristics see Chapter 14.
Table 2 AGC threshold values
MODE
256, 64, 16 and 4-QAM
32-QAM
ATH (AGC THRESHOLD)
2040
1442
I²C-BUS DATA FOR ADDRESS 08
7F
5A
handbook, full pagewidth
external
DIN8
to
DIN0
I²C-BUS
IBIAS
AGC
DETECTOR
I²C-BUS
BIAS
GENERATOR
DAC
rs Iref2
IAGC
Vref
Iref2
ADC
I²C-BUS
to AGC
amplifier
MGG173
Fig.13 AGC schematic diagram.
1996 Nov 19
17