TDA4853 Datasheet, PDF (9/60 Pages) NXP Semiconductors – I2C-bus autosync deflection controllers for PC/TV monitors

Philips Semiconductors
I²C-bus autosync deflection controllers for
PC/TV monitors
Product specification
TDA4853; TDA4854
Horizontal oscillator
The horizontal oscillator is of the relaxation type and
requires a capacitor of 10 nF to be connected at HCAP
(pin 29). For optimum jitter performance the value of 10 nF
must not be changed.
The minimum oscillator frequency is determined by a
resistor connected between pin HREF and ground.
A resistor connected between pins HREF and HBUF
defines the frequency range.
The reference current at pin HREF also defines the
integration time constant of the vertical sync integration.
Calculation of line frequency range
The oscillator frequencies f_min and f_max must first be
calculated. This is achieved by adding the spread of the
relevant components to the highest and lowest sync
frequencies f_sync(min) and f_sync(max). The oscillator is driven
by the currents in R_HREF and R_HBUF.
The following example is a 31.45 to 90 kHz application:
Table 1 Calculation of total spread
spread of
IC
C_HCAP
R_HREF, R_HBUF
Total
for f_max
±3%
±2%
±2%
±7%
for f_min
±5%
±2%
±2%
±9%
The resistor R_HBUFpar is calculated as the value of R_HREF
and R_HBUF in parallel. The formulae for R_HBUF also takes
into account the voltage swing across this resistor
R_HBUF = ^R-R----HH---^RR----^EE---^FF----^×_–-----RR----_HH---_B-^B--_U-^U---_FF--_p-^p--_aa--_rr × 0.8 = 805 Ω
PLL1 phase detector
The phase detector is a standard type using switched
current sources, which are independent of the horizontal
frequency. It compares the middle of the horizontal sync
with a fixed point on the oscillator sawtooth voltage.
The PLL1 loop filter is connected to HPLL1 (pin 26).
See also Section “Horizontal position adjustment and
corrections”.
Horizontal position adjustment and corrections
A linear adjustment of the relative phase between the
horizontal sync and the oscillator sawtooth (in PLL1 loop)
is achieved via register HPOS. Once adjusted, the relative
phase remains constant over the whole frequency range.
Correction of pin unbalance and parallelogram is achieved
by modulating the phase between the oscillator sawtooth
and horizontal flyback (in loop PLL2) via registers
HPARAL and HPINBAL. If those asymmetric EW
corrections are performed in the deflection stage, both
registers can be disconnected from the horizontal phase
via control bit ACD. This does not change the output at
pin ASCOR.
Thus the typical frequency range of the oscillator in this
example is:
f_max = f_sync(max) × 1.07 = 96.3 kHz
f_min = -f-^s---^y-1--ⁿ--.^c-0--⁽--9^m----ⁱ-ⁿ--⁾ = 28.9 kHz
The TV mode is centred around f_min with a control range of
±10%. Activation of the TV mode is only allowed between
15.625 and 35 kHz.
The resistors R_HREF and R_HBUFpar can be calculated using
the following formulae:
R_HREF = -f-_m----_i-_n----₊---7--0--8-.--0-^×--0---k-1---H2-----z_×----^×-f--_m2--k--_i-_n^Ω--_[---k---H-----z----_] = 2.61 kΩ
R_HBUFpar = -f-_m----_a---_x---₊---7--0--8--.-0--^×--0--k-1---H2-----z_×----^×-f--_m2--k--_a--^Ω_x---_[--k----H-----z----_] = 726 Ω
Horizontal moire cancellation
To achieve a cancellation of horizontal moire (also known
as ‘video moire’), the horizontal frequency is
divided-by-two to achieve a modulation of the horizontal
phase via PLL2. The amplitude is controlled by
register HMOIRE. To avoid a visible structure on screen
the polarity changes with half of the vertical frequency.
Control bit MOD disables the moire cancellation function.
1999 Jul 13
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