TDA4853 Datasheet, PDF (16/60 Pages) NXP Semiconductors – I2C-bus autosync deflection controllers for PC/TV monitors

Philips Semiconductors
I²C-bus autosync deflection controllers for
PC/TV monitors
Product specification
TDA4853; TDA4854
CHARACTERISTICS
V_CC = 12 V; T_amb = 25 °C; peripheral components in accordance with Figs 1 and 2; unless otherwise specified.
SYMBOL
PARAMETER
CONDITIONS
MIN. TYP. MAX. UNIT
Horizontal sync separator
INPUT CHARACTERISTICS FOR DC-COUPLED TTL SIGNALS: PIN HSYNC
V_i(HSYNC)
V_HSYNC(sl)
t_r(HSYNC)
t_f(HSYNC)
t_{W(HSYNC)(min)}
I_i(HSYNC)
sync input signal voltage
slicing voltage level
rise time of sync pulse
fall time of sync pulse
minimum width of sync pulse
input current
V_HSYNC = 0.8 V
V_HSYNC = 5.5 V
1.7
−
−
V
1.2
1.4
1.6
V
10
−
500
ns
10
−
500
ns
0.7
−
−
µs
−
−
−200 µA
−
−
10
µA
INPUT CHARACTERISTICS FOR AC-COUPLED VIDEO SIGNALS (SYNC-ON-VIDEO, NEGATIVE SYNC POLARITY)
V_HSYNC
sync amplitude of video input R_source = 50 Ω
signal voltage
−
300
−
mV
V_HSYNC(sl)
slicing voltage level
(measured from top sync)
R_source = 50 Ω
90
120
150
mV
V_clamp(HSYNC)
top sync clamping voltage level R_source = 50 Ω
1.1
1.28 1.5
V
I_ch(HSYNC)
charge current for coupling
V_HSYNC > V_clamp(HSYNC)
1.7
2.4
3.4
µA
capacitor
t_{W(HSYNC)(min)}
R_source(max)
R_{i(diff)(HSYNC)}
minimum width of sync pulse
maximum source resistance
differential input resistance
duty cycle = 7%
during sync
0.7
−
−
−
−
80
−
µs
1500 Ω
−
Ω
Automatic polarity correction for horizontal sync
t--_{P--t--(H--H---)}
horizontal sync pulse width
related to line period
−
−
25
%
t_d(HPOL)
delay time for changing polarity
0.3
−
1.8
ms
Vertical sync integrator
t_int(V)
integration time for generation
of a vertical trigger pulse
f_H = 15.625 kHz;
I_HREF = 0.52 mA
f_H = 31.45 kHz;
I_HREF = 1.052 mA
f_H = 64 kHz;
I_HREF = 2.141 mA
f_H = 100 kHz;
I_HREF = 3.345 mA
14
20
26
µs
7
10
13
µs
3.9
5.7
6.5
µs
2.5
3.8
4.5
µs
Vertical sync slicer (DC-coupled, TTL compatible): pin VSYNC
V_i(VSYNC)
V_VSYNC(sl)
I_i(VSYNC)
sync input signal voltage
slicing voltage level
input current
0 V < V_SYNC < 5.5 V
1.7
−
−
V
1.2
1.4
1.6
V
−
−
±10
µA
1999 Jul 13
16