TDA4853 Datasheet, PDF (13/60 Pages) NXP Semiconductors – I2C-bus autosync deflection controllers for PC/TV monitors

Philips Semiconductors
I²C-bus autosync deflection controllers for
PC/TV monitors
Product specification
TDA4853; TDA4854
TDA4854: dynamic focus section [FOCUS (pin 32)]
This section generates a complete drive signal for dynamic
focus applications. The amplitude of the horizontal
parabola is internally stabilized, thus it is independent of
the horizontal frequency. The amplitude can be adjusted
via register HFOCUS. Changing horizontal size may
require a correction of HFOCUS. To compensate for the
delay in external focus amplifiers a ‘pre-correction’ for the
phase of the horizontal parabola has been implemented.
The amplitude of the vertical parabola is independent of
frequency and tracks with all vertical adjustments.
The amplitude can be adjusted via register VFOCUS.
FOCUS (pin 32) is designed as a voltage output for the
superimposed vertical and horizontal parabolas.
B+ control function block
The B+ control function block of the TDA4853; TDA4854
consists of an Operational Transconductance Amplifier
(OTA), a voltage comparator, a flip-flop and a discharge
circuit. This configuration allows easy applications for
different B+ control concepts. See also Application Note
AN96052: “B+ converter Topologies for Horizontal
Deflection and EHT with TDA4855/58”.
GENERAL DESCRIPTION
The non-inverting input of the OTA is connected internally
to a high precision reference voltage. The inverting input is
connected to BIN (pin 5). An internal clamping circuit limits
the maximum positive output voltage of the OTA.
The output itself is connected to BOP (pin 3) and to the
inverting input of the voltage comparator.
The non-inverting input of the voltage comparator can be
accessed via BSENS (pin 4).
B+ drive pulses are generated by an internal flip-flop and
fed to BDRV (pin 6) via an open-collector output stage.
This flip-flop is set at the rising edge of the signal at HDRV
(pin 8). The falling edge of the output signal at BDRV has
a defined delay of t_d(BDRV) to the rising edge of the HDRV
pulse (see Fig.23). When the voltage at BSENS exceeds
the voltage at BOP, the voltage comparator output resets
the flip-flop and, therefore, the open-collector stage at
BDRV is floating again.
An internal discharge circuit allows a well defined
discharge of capacitors at BSENS. BDRV is active at a
LOW-level output voltage (see Figs 23 and 24), thus it
requires an external inverting driver stage.
The B+ function block can be used for B+ deflection
modulators in many different ways. Two popular
application combinations are as follows:
• Boost converter in feedback mode (see Fig.23)
In this application the OTA is used as an error amplifier
with a limited output voltage range. The flip-flop is set on
the rising edge of the signal at HDRV. A reset will be
generated when the voltage at BSENS, taken from the
current sense resistor, exceeds the voltage at BOP.
If no reset is generated within a line period. The rising
edge of the next HDRV pulse forces the flip-flop to reset.
The flip-flop is set immediately after the voltage at
BSENS has dropped below the threshold voltage
V_{RESTART(BSENS)}.
• Buck converter in feed forward mode (see Fig.24)
This application uses an external RC combination at
BSENS to provide a pulse width which is independent
from the horizontal frequency. The capacitor is charged
via an external resistor and discharged by the internal
discharge circuit. For normal operation the discharge
circuit is activated when the flip-flop is reset by the
internal voltage comparator. The capacitor will now be
discharged with a constant current until the internally
controlled stop level V_STOP(BSENS) is reached. This level
will be maintained until the rising edge of the next HDRV
pulse sets the flip-flop again and disables the discharge
circuit.
If no reset is generated within a line period, the rising
edge of the next HDRV pulse automatically starts the
discharge sequence and resets the flip-flop. When the
voltage at BSENS reaches the threshold voltage
V_{RESTART(BSENS)}, the discharge circuit will be disabled
automatically and the flip-flop will be set immediately.
This behaviour allows a definition of the maximum duty
cycle of the B+ control drive pulse by the relationship of
charge current to discharge current.
Supply voltage stabilizer, references, start-up
procedures and protection functions
The TDA4853; TDA4854 provides an internal supply
voltage stabilizer for excellent stabilization of all internal
references. An internal gap reference, especially designed
for low-noise, is the reference for the internal horizontal
and vertical supply voltages. All internal reference currents
and drive current for the vertical output stage are derived
from this voltage via external resistors.
If either the supply voltage is below 8.3 V or no data from
the I²C-bus has been received after power-up, the internal
soft start and protection functions do not allow any of those
outputs [HDRV, BDRV, VOUT1, VOUT2 and HUNLOCK
(see Fig.25)] to be active.
1999 Jul 13
13