TDA4853 Datasheet, PDF (43/60 Pages) NXP Semiconductors – I2C-bus autosync deflection controllers for PC/TV monitors

Philips Semiconductors
I²C-bus autosync deflection controllers for
PC/TV monitors
PLL2 soft start sequence and PLL2 soft-down sequence
Product specification
TDA4853; TDA4854
handbook, full pagewidth
VHPLL2
MGM084
4.7 V
continuous blanking off
PLL2 enabled
frequency detector enabled
HDRV/HFLB protection enabled
duty ^{cycle increases}
3.4 V BDRV duty cycle has reached nominal value
2.8 V BDRV duty cycle begins to increase
HDRV duty cycle has reached nominal value
1.7 V HDRV duty cycle begins to increase
1 V VOUT1 and VOUT2 enabled
time
a. PLL2 soft start sequence, via the I²C-bus, if V_CC > 8.6 V.
handbook, full pagewidth
VHPLL2
MGM085
4.7 V
continuous blanking (pin 16 and 17) activated
PLL2 disabled
frequency detector disabled
HDRV/HFLB protection disabled
3.4 V BDRV duty cycle begins to decrease⁽¹⁾
duty _{cycle decreases}
2.8 V
BDRV floating
HDRV duty cycle begins to decrease⁽¹⁾
1.7 V HDRV floating
1 V VOUT1 and VOUT2 floating
time
b. PLL2 soft-down sequence, via the I²C-bus, if V_CC > 8.6 V.
(1) HDRV, BDRV, VOUT2 and VOUT1 are floating for V_CC < 8.6 V.
Fig.26 PLL2 soft start sequence and PLL2 soft-down sequence via the I²C-bus.
1999 Jul 13
43