TDA4853 Datasheet, PDF (26/60 Pages) NXP Semiconductors – I2C-bus autosync deflection controllers for PC/TV monitors

Philips Semiconductors
I²C-bus autosync deflection controllers for
PC/TV monitors
Product specification
TDA4853; TDA4854
SYMBOL
PARAMETER
CONDITIONS
MIN. TYP. MAX. UNIT
V_off(VCC)
supply voltage level for
deactivation of BDRV, VOUT1,
VOUT2 and HUNLOCK; also
sets register SOFTST
V_CC decreasing from
above typical 8.3 V
7.7
8.1
8.5
V
THRESHOLDS DERIVED FROM HPLL2 VOLTAGE
V_{HPLL2(blank)(ul)}
upper limit voltage for
continuous blanking
V_{HPLL2(bduty)(ul)}
upper limit voltage for variation
of BDRV duty cycle
V_{HPLL2(bduty)(ll)}
lower limit voltage for variation
of BDRV duty cycle
V_{HPLL2(hduty)(ul)}
upper limit voltage for variation
of HDRV duty cycle
V_{HPLL2(hduty)(ll)}
lower limit voltage for variation
of HDRV duty cycle
V_{HPLL2(stby)(ll)}
lower limit voltage for VOUT1
and VOUT2 to be active via
I²C-bus soft start
V_{HPLL2(stby)(ul)}
upper limit voltage for standby
voltage
V_{HPLL2(stby)(ll)}
lower limit voltage for VOUT1
and VOUT2 to be active via
external DC current
−
4.7
−
V
−
3.4
−
V
−
2.8
−
V
−
2.8
−
V
−
1.7
−
V
−
1.1
−
V
−
1
−
V
−
0
−
V
Notes
1. For duration of vertical blanking pulse see subheading ‘Vertical oscillator [oscillator frequency in application without
adjustment of free-running frequency f_fr(V)]’.
2. Continuous blanking at CLBL (pin 16) will be activated, if one of the following conditions is true:
a) No horizontal flyback pulses at HFLB (pin 1) within a line
b) X-ray protection is triggered
c) Voltage at HPLL2 (pin 30) is low during soft start
d) Supply voltage at V_CC (pin 10) is low
e) PLL1 unlocked while frequency-locked loop is in search mode.
3. Oscillator frequency is f_min when no sync input signal is present (continuous blanking at pins 16 and 17).
4. Loading of HPLL1 (pin 26) is not allowed.
5. Voltage at HPLL1 (pin 26) is fed to HBUF (pin 27) via a buffer. Disturbances caused by horizontal sync are removed
by an internal sample-and-hold circuit.
6. All vertical and EW adjustments in accordance with note 8, but VSIZE = 80% (register VSIZE = 63 and control
bit VOVSCN = 0).
7. Value of resistor at VREF (pin 23) may not be changed.
8. All vertical and EW adjustments are specified at nominal vertical settings; unless otherwise specified, which means:
a) VSIZE = 100% (register VSIZE = 127 and control bit VOVSCN = 0)
b) VSMOD = 0 (no EHT compensation)
1999 Jul 13
26