BUK116-50L Datasheet, PDF (9/13 Pages) NXP Semiconductors – Logic level TOPFET SMD version of BUK106-50L/S

Philips Semiconductors
Logic level TOPFET
SMD version of BUK106-50L/S
Product specification
BUK116-50L/S
VDDP(P) / V
50
BUK116-50L/S
40
max
30
20
10
0
0
2
4
6
8
10
VIS / V
Fig.16. Maximum drain source supply voltage for
SC load protection. V_DDP(P) = f(V_IS); T_mb ≤ 150 ˚C
VPSP / V
10
BUK116-50L/S
8
min
6
BUK116-50S
4
BUK116-50L
2
0
0
2
4
6
8
10
VIS / V
Fig.17. Minimum protection supply voltage
for SC load protection. V_PSP = f(V_IS); T_mb ≥ 25 ˚C
td sc / ms
10
BUK116-50L/S
1
PDSM
0.1
0.01
0.1
1
10
PD / kW
Fig.18. Typical overload protection characteristics.
t_{d sc} = f(P_DS); conditions: V_PS ≥ V_PSP; V_IS ≥ 5 V
Energy & Time
1.0
BUK116-50L/S
0.8
Energy / J
0.6
0.4
Time / ms
0.2
Tj(TO)
0
-60
-20
20
60 100 140 180 220
Tmb / C
Fig.19. Typical overload protection characteristics.
Conditions: V_DD = 13 V; V_PS = V_PSN, V_IS = 8 V; SC load
ESC(TO) / J
1.6
BUK116-50L/S
1.4
1.2
BUK116-50L
VIS / V =
1.0
5
0.8
10
0.6
5
10
0.4
0.2
BUK116-50S
0
0
2
4
6
8
10
VPS / V
Fig.20. Typical overload protection energy, T_j = 25 ˚C
E_SC(TO) = f(V_PS); conditions: V_DS = 13 V, parameter V_IS
ID / A
50
BUK116-50L/S
40
30
typ.
20
10
0
50
60
70
VDS / V
Fig.21. Typical clamping characteristics, 25 ˚C.
I_D = f(V_DS); conditions: R_IS = 100 Ω; t_p ≤ 50 µs
July 1996
9
Rev 1.000