BUK116-50L Datasheet, PDF (10/13 Pages) NXP Semiconductors – Logic level TOPFET SMD version of BUK106-50L/S

Philips Semiconductors
Logic level TOPFET
SMD version of BUK106-50L/S
Product specification
BUK116-50L/S
VIS(TO) / V
2
1
max.
typ.
min.
0
-60 -40 -20 0 20 40 60 80 100 120 140
Tj / C
Fig.22. Input threshold voltage.
V_IS(TO) = f(T_j); conditions: I_D = 1 mA; V_DS = 5 V
IPS / mA
1.0
BUK116-50L/S
0.5
0
0
2
4
6
8
10
12
14
VPS / V
Fig.23. Typical DC protection supply characteristics.
I_PS = f(V_PS); normal or overload operation; T_j = 25 ˚C
IISL / mA
150
100
50
VPS / V = 11
BUK116-50L/S
10
9
8
7
6
5
4
0
0
2
4
6
8
10
VIS / V
Fig.24. Typical latched input characteristics, 25 ˚C.
I_ISL = f(V_IS); after overload protection latched
IS / A
200
BUK116-50L/S
150
100
50
0
0 0.2 0.4 0.6 0.8 1 1.2 1.4 1.6 1.8 2
VSD / V
Fig.25. Typical reverse diode current, T_j = 25 ˚C.
I_S = f(V_SDS); conditions: V_IS = 0 V; t_p = 250 µs
EDSM%
120
110
100
90
80
70
60
50
40
30
20
10
0
0
20
40
60
80 100 120 140
Tmb / C
Fig.26. Normalised limiting clamping energy.
E_DSM% = f(T_mb); conditions: I_D = 27 A
VDS
0
ID
0
VIS
0
V(CL)DSR
VDD
L
+ ^VDD
RF
RI = RIS
+ ^VPS
P
F
P
I
VDS
D
TOPFET
D.U.T.
S
-
R 01
shunt
-ID/100
Fig.27. Clamping energy test circuit, R_IS = 100 Ω.
E_DSM = 0.5 ⋅ L I_D² ⋅ V_(CL)DSR/(V_(CL)DSR − V_DD)
July 1996
10
Rev 1.000