74HC_HCT259_15 Datasheet, PDF (9/22 Pages) NXP Semiconductors – 8-bit addressable latch

NXP Semiconductors
74HC259; 74HCT259
8-bit addressable latch
Table 8. Dynamic characteristics …continued
Voltages are referenced to GND (ground = 0 V); for test circuit see Figure 12.
Symbol Parameter
Conditions
25 C
40 C to +85 C 40 C to +125 C Unit
Min Typ^[1] Max Min Max
Min
Max
t_su
set-up time D, An to LE;
see Figure 10 and
Figure 11
V_CC = 2.0 V
80 19 - 100
-
120
- ns
V_CC = 4.5 V
16 7
-
20
-
24
- ns
V_CC = 6.0 V
14 6
-
17
-
20
- ns
t_h
hold time
D to LE; see Figure 10
and Figure 11
V_CC = 2.0 V
V_CC = 4.5 V
V_CC = 6.0 V
0 19 -
0
-
0
- ns
0 6 -
0
-
0
- ns
0 5 -
0
-
0
- ns
An to LE; see Figure 10
and Figure 11
V_CC = 2.0 V
V_CC = 4.5 V
2 11 -
2
-
2
- ns
2 4 -
2
-
2
- ns
V_CC = 6.0 V
C_PD
power
f_i = 1 MHz;
dissipation
V_I = GND to V_CC
capacitance
2 3 -
2
-
2
- ns
[4] _-
19
-
-
-
-
- pF
74HCT259
t_pd
propagation D to Qn; see Figure 6
[2]
delay
V_CC = 4.5 V
- 23 39
-
49
-
59 ns
V_CC = 5.0 V; C_L = 15 pF
- 20 -
-
-
-
- ns
An to Qn; see Figure 7
[2]
V_CC = 4.5 V
- 25 41
51
62 ns
V_CC = 5.0 V; C_L = 15 pF
- 20 -
-
-
-
- ns
LE to Qn; see Figure 8
[2]
V_CC = 4.5 V
- 22 38
-
48
-
57 ns
V_CC = 5.0 V; C_L = 15 pF
- 20 -
-
-
-
- ns
t_PHL
HIGH to LOW MR to Qn; see Figure 9
propagation
delay
V_CC = 4.5 V
- 23 39
-
49
-
59 ns
V_CC = 5.0 V; C_L = 15 pF
- 20 -
-
-
-
- ns
t_t
transition time see Figure 8
[3]
V_CC = 4.5 V
-
7 15
-
19
-
22 ns
t_W
pulse width LE HIGH or LOW;
see Figure 8
V_CC = 4.5 V
19 11 -
24
-
29
- ns
MR LOW; see Figure 9
V_CC = 4.5 V
18 10 -
23
-
27
- ns
74HC_HCT259
Product data sheet
All information provided in this document is subject to legal disclaimers.
Rev. 5 — 7 August 2012
© NXP B.V. 2012. All rights reserved.
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