74HC_HCT259_15 Datasheet, PDF (2/22 Pages) NXP Semiconductors – 8-bit addressable latch

NXP Semiconductors
74HC259; 74HCT259
8-bit addressable latch
 ESD protection:
 HBM JESD22-A114F exceeds 2000 V
 MM JESD22-A115-A exceeds 200 V
 CDM JESD22E exceeds 1000 V
 Multiple package options
 Specified from 40 C to +85 C and from 40 C to +125 C
3. Ordering information
Table 1. Ordering information
Type number Package
Temperature range Name
74HC259N
40 C to +125 C DIP16
74HCT259N
74HC259D
40 C to +125 C SO16
74HCT259D
74HC259DB
40 C to +125 C SSOP16
74HCT259DB
74HC259PW 40 C to +125 C TSSOP16
74HCT259PW
74HC259BQ
40 C to +125 C DHVQFN16
74HCT259BQ
Description
plastic dual in-line package; 16 leads (300 mil)
Version
SOT38-4
plastic small outline package; 16 leads;
body width 3.9 mm
SOT109-1
plastic shrink small outline package; 16 leads; body SOT338-1
width 5.3 mm
plastic thin shrink small outline package; 16 leads;
body width 4.4 mm
SOT403-1
plastic dual in-line compatible thermal enhanced very SOT763-1
thin quad flat package; no leads; 16 terminals;
body 2.5  3.5  0.85 mm
4. Functional diagram
14
LE
Q0 ⁴
13 _D
Q1 ⁵
Q2 ⁶
Q3 ⁷
1 _A0
9
Q4
2
A1
10
Q5
3
A2
11
Q6
12
Q7
MR
15 mna573
Fig 1. Logic symbol
13 _Z9
15
G8
14
G10
DX
9,10D
4
1
0
1
C10
8R
0
2
3
G
0
7
1
2
5
6
2
7
3
9
4
10
5
11
6
12
7
mna572
Fig 2. IEC logic symbol
74HC_HCT259
Product data sheet
All information provided in this document is subject to legal disclaimers.
Rev. 5 — 7 August 2012
© NXP B.V. 2012. All rights reserved.
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