74HC_HCT259_15 Datasheet, PDF (4/22 Pages) NXP Semiconductors – 8-bit addressable latch

NXP Semiconductors
74HC259; 74HCT259
8-bit addressable latch
5.2 Pin description
Table 2. Pin description
Symbol
Pin
Description
A0, A1, A2
1, 2, 3
address input
Q0, Q1, Q2, Q3, Q4, Q5, Q6, Q7 4, 5, 6, 7, 9, 10, 11, 12 latch output
GND
8
ground (0 V)
D
13
data input
LE
14
latch enable input (active LOW)
MR
15
conditional reset input (active LOW)
V_CC
16
supply voltage
6. Functional description
Table 3. Function table^[1]
Operating mode
Input
MR LE D
Reset (clear)
L HX
Demultiplexer
LLd
(active HIGH 8-channel) _{L L d}
decoder (when D = H)
LLd
LLd
LLd
LLd
LLd
LLd
Memory (no action)
HHX
Addressable latch
HL d
HL d
HL d
HL d
HL d
HL d
HL d
HL d
Output
A0 A1 A2 Q0 Q1 Q2 Q3 Q4 Q5 Q6 Q7
XXXL
L
L
L
L
L
L
L
L L L Q=d L
L
L
L
L
L
L
HL L L
Q=d L
L
L
L
L
L
L HL L
L
Q=d L
L
L
L
L
HHL L
L
L
Q=d L
L
L
L
L L HL
L
L
L
Q=d L
L
L
HL HL
L
L
L
L
Q=d L
L
L HHL
L
L
L
L
L
Q=d L
HHHL
L
L
L
L
L
L
Q=d
X X X q₀
q₁
q₂
q₃
q₄
q₅
q₆
q₇
L
L
L Q = d q₁
q₂
q₃
q₄
q₅
q₆
q₇
H L L q₀
Q = d q₂
q₃
q₄
q₅
q₆
q₇
L
H L q₀
q₁
Q = d q₃
q₄
q₅
q₆
q₇
HHL
q₀
q₁
q₂
Q = d q₄
q₅
q₆
q₇
L
L H q₀
q₁
q₂
q₃
Q = d q₅
q₆
q₇
H L H q₀
q₁
q₂
q₃
q₄
Q = d q₆
q₇
L
H H q₀
q₁
q₂
q₃
q₄
q₅
Q = d q₇
H H H q₀
q₁
q₂
q₃
q₄
q₅
q₆
Q=d
[1] H = HIGH voltage level;
L = LOW voltage level;
X = don’t care;
d = HIGH or LOW data one set-up time prior to the LOW-to-HIGH LE transition;
q = lower case letter indicates the state of the referenced input one set-up time prior to the LOW-to-HIGH transition.
74HC_HCT259
Product data sheet
All information provided in this document is subject to legal disclaimers.
Rev. 5 — 7 August 2012
© NXP B.V. 2012. All rights reserved.
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