ISP1161 Datasheet, PDF (89/127 Pages) NXP Semiconductors – Full-speed Universal Serial Bus single-chip host and device controller

Philips Semiconductors
ISP1161
Full-speed USB single-chip host and device controller
Table 74: Command and register summary…continued
Name
Destination
Read Chip ID
Chip ID Register
Read Interrupt Register
Interrupt Register
Code (Hex)
B5
C0
Transaction ^[1]
read 1 word
read 2 words
[1] With N representing the number of bytes, the number of words for 16-bit bus width is: (N + 1) DIV 2.
[2] Validating an OUT endpoint buffer causes unpredictable behavior of ISP1161’s DC.
[3] Clearing an IN endpoint buffer causes unpredictable behavior of ISP1161’s DC.
[4] Reads a copy of the Status Register: executing this command does not clear any status bits or interrupt bits.
[5] When accessing an 8-bit register in 16-bit mode, the upper byte is invalid.
[6] During isochronous transfer in 16-bit mode, because N ≤ 1023, the firmware must take care of the upper byte.
14.1 Initialization commands
Initialization commands are used during the enumeration process of the USB
network. These commands are used to configure and enable the embedded
endpoints. They also serve to set the USB assigned address of ISP1161’s DC and to
perform a device reset.
14.1.1 Write/Read Endpoint Configuration
This command is used to access the Endpoint Configuration Register (ECR) of the
target endpoint. It defines the endpoint type (isochronous or bulk/interrupt), direction
(OUT/IN), FIFO size and buffering scheme. It also enables the endpoint FIFO. The
register bit allocation is shown in Table 75. A bus reset will disable all endpoints.
The allocation of FIFO memory only takes place after all 16 endpoints have been
configured in sequence (from endpoint 0 OUT to endpoint 14). Although the control
endpoints have fixed configurations, they must be included in the initialization
sequence and be configured with their default values (see Table 7). Automatic FIFO
allocation starts when endpoint 14 has been configured.
Remark: If any change is made to an endpoint configuration which affects the
allocated memory (size, enable/disable), the FIFO memory contents of all endpoints
becomes invalid. Therefore, all valid data must be removed from enabled endpoints
before changing the configuration.
Code (Hex): 20 to 2F — write (control OUT, control IN, endpoint 1 to 14)
Code (Hex): 30 to 3F — read (control OUT, control IN, endpoint 1 to 14)
Transaction — write/read 1 word
Table 75: Endpoint Configuration Register: bit allocation
Bit
7
6
5
4
3
2
1
0
Symbol
FIFOEN
EPDIR
DBLBUF FFOISO
FFOSZ[3:0]
Reset
0
0
0
0
0
0
0
0
Access
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
9397 750 08313
Product data
Rev. 01 — 3 July 2001
© Philips Electronics N.V. 2001. All rights reserved.
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