ISP1161 Datasheet, PDF (111/127 Pages) NXP Semiconductors – Full-speed Universal Serial Bus single-chip host and device controller

Philips Semiconductors
ISP1161
Full-speed USB single-chip host and device controller
20.2 Parallel I/O timing
Table 116:Dynamic characteristics: parallel interface timing
Symbol
Parameter
Read timing
t_SHSL
first RD/WR after CMD
t_SLRL
CS LOW to RD LOW
t_RHSH
RD HIGH to CS HIGH
t_RL
RD LOW pulse width
t_RHRL
t_RC
RD HIGH to next RD LOW
RD cycle
t_RHDZ
RD data hold time
t_RLDV
RD LOW to data valid
Write timing
t_WL
WR LOW pulse width
t_WHWL
WR HIGH to next WR LOW
t_WC
WR cycle
t_SLWL
CS LOW to WR LOW
t_WHSH
t_WDSU
WR HIGH to CS HIGH
WR data setup time
t_WDH
WR data hold time
Conditions
16-bit bus
Unit
Min
Max
300
-
ns
0
-
ns
0
-
ns
33
-
ns
110
-
ns
143
-
ns
3
-
ns
32
-
ns
26
-
ns
110
-
ns
136
-
ns
0
-
ns
0
-
ns
5
-
ns
8
-
CS
A0
RD
D [15:0]
t _SHSL
t _SLRL
t _RHRL
t _RL
t _RC
t _SLWL
t _RHSH
t _WHSH
t _RLDV
data
valid
t _WL
data
valid
t _WHWL
t _WC
data
valid
t _RHDZ
data
valid
WR
D[15:0]
data
valid
data
valid
t _WDH
data
valid
Fig 45. 16-bit microprocessor parallel I/O interface timing.
data
valid
t _WDSU
data
valid
MGT969
9397 750 08313
Product data
Rev. 01 — 3 July 2001
© Philips Electronics N.V. 2001. All rights reserved.
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