ISP1161 Datasheet, PDF (113/127 Pages) NXP Semiconductors – Full-speed Universal Serial Bus single-chip host and device controller

Philips Semiconductors
ISP1161
Full-speed USB single-chip host and device controller
20.3.2 HC multi-cycle burst mode DMA timing
Table 118:Dynamic characteristics: HC multi-cycle burst mode DMA timing
Symbol
Parameter
Conditions
Read/write timing (for 4-cycle and 8-cycle burst mode)
t_RL
WR/RD LOW pulse width
t_RHRL
WR/RD HIGH to next WR/RD
LOW
t_RC
WR/RD cycle
t_SLRL
RD/WR LOW to DREQ1 LOW
t_SHAH
RD/WR HIGH to DACK1 HIGH
t_RHAL
DREQ1 HIGH to DACK1 LOW
t_DC
t_DS(read)
DREQ1 cycle
DREQ1 pulse spacing (read) 4-cycle burst mode
t_DS(read)
t_DS(write)
DREQ1 pulse spacing (read) 8-cycle burst mode
DREQ1 pulse spacing (write) 4-cycle burst mode
t_DS(write)
DREQ1 pulse spacing (write) 8-cycle burst mode
[1] t_SLAL + (4 or 8)t_RC + t_DS.
16-bit bus
Min
Max
42
-
60
-
102
-
22
64
>0
-
>0
[1]
-
105
-
150
-
62 to 84 -
150 to 167 -
Unit
ns
ns
ns
ns
ns
ns
ns
ns
DREQ1
t _RHSH
t _SLAL
DACK1
RD or WR
t _RHRL
t _RL
t _RC
Fig 47. HC multi-cycle burst mode DMA timing.
t _DS
t _SLRL
t _SHAH
MGT971
9397 750 08313
Product data
Rev. 01 — 3 July 2001
© Philips Electronics N.V. 2001. All rights reserved.
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