ISP1161 Datasheet, PDF (49/127 Pages) NXP Semiconductors – Full-speed Universal Serial Bus single-chip host and device controller

Philips Semiconductors
ISP1161
Full-speed USB single-chip host and device controller
Table 10: Endpoint selection for DMA transfer…continued
Endpoint
identifier
EPIDX[3:0]
Transfer direction
EPDIR = 0
EPDIR = 1
11
1100
OUT: read
IN: write
12
1101
OUT: read
IN: write
13
1110
OUT: read
IN: write
14
1111
OUT: read
IN: write
12.2 8237 compatible mode
The 8237 compatible DMA mode is selected by clearing bit DAKOLY in the Hardware
Configuration Register (see Table 81). The pin functions for this mode are shown in
Table 11.
Table 11: 8237 compatible mode: pin functions
Symbol Description
I/O
Function
DREQ2 DC’s DMA request
O
ISP1161 DC requests a DMA transfer
DACK2 DC’s DMA
I
DMA controller confirms the transfer
acknowledge
EOT
end of transfer
I
DMA controller terminates the transfer
RD
read strobe
I
instructs ISP1161 DC to put data on the
bus
WR
write strobe
I
instructs ISP1161 DC to get data from the
bus
The DMA subsystem of an IBM compatible PC is based on the Intel 8237 DMA
controller. It operates as a ‘fly-by’ DMA controller: the data is not stored in the DMA
controller, but it is transferred between an I/O port and a memory address. A typical
example of ISP1161 DC in 8237 compatible DMA mode is given in Figure 38.
The 8237 has two control signals for each DMA channel: DREQ (DMA Request) and
DACK (DMA Acknowledge). General control signals are HRQ (Hold Request), HLDA
(Hold Acknowledge) and EOP (End-Of-Process). The bus operation is controlled via
MEMR (Memory Read), MEMW (Memory Write), IOR (I/O read) and IOW (I/O write).
9397 750 08313
Product data
D0 to D15
ISP1161
DEVICE
CONTROLLER
DREQ2
DACK2
RAM
MEMR
MEMW
DMA
CONTROLLER
8237
DREQ
HRQ
DACK
HLDA
CPU
HRQ
HLDA
RD
IOR
WR
IOW
004aaa009
Fig 38. ISP1161’s device controller in 8237 compatible DMA mode.
Rev. 01 — 3 July 2001
© Philips Electronics N.V. 2001. All rights reserved.
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