ISP1161 Datasheet, PDF (51/127 Pages) NXP Semiconductors – Full-speed Universal Serial Bus single-chip host and device controller

Philips Semiconductors
ISP1161
Full-speed USB single-chip host and device controller
Table 12: DACK-only mode: pin functions…continued
Symbol Description
I/O
Function
EOT
End-Of-Transfer
I
DMA controller terminates the transfer
RD
read strobe
I
not used
WR
write strobe
I
not used
In DACK-only mode the ISP1161 DC uses the DACK2 signal as a data strobe. Input
signals RD and WR are ignored. This mode is used in CPU systems that have a
single address space for memory and I/O access. Such systems have no separate
MEMW and MEMR signals: the RD and WR signals are also used as memory data
strobes.
ISP1161
DEVICE
CONTROLLER
DREQ2
DACK2
D0 to D15
RAM
DMA
CONTROLLER
DREQ
DACK
RD
WR
HRQ
HLDA
Fig 39. ISP1161’s device controller in DACK-only DMA mode.
CPU
HRQ
HLDA
004aaa010
12.4 End-Of-Transfer conditions
12.4.1 Bulk endpoints
A DMA transfer to/from a bulk endpoint can be terminated by any of the following
conditions (bit names refer to the DMA Configuration Register, see Table 85):
• An external End-Of-Transfer signal occurs on input EOT
• The internal DMA Counter Register reaches zero (CNTREN = 1)
• A short/empty packet is received on an enabled OUT endpoint (SHORTP = 1)
• DMA operation is disabled by clearing bit DMAEN.
External EOT: When reading from an OUT endpoint, an external EOT will stop the
DMA operation and clear any remaining data in the current FIFO. For a double-
buffered endpoint the other (inactive) buffer is not affected.
When writing to an IN endpoint, an EOT will stop the DMA operation and the data
packet in the FIFO (even if it is smaller than the maximum packet size) will be sent to
the USB host at the next IN token.
DMA Counter Register zero: An EOT from the DMA Counter Register is enabled by
setting bit CNTREN in the DMA Configuration Register. The ISP1161 has a 16-bit
DMA Counter Register, which specifies the number of bytes to be transferred. When
9397 750 08313
Product data
Rev. 01 — 3 July 2001
© Philips Electronics N.V. 2001. All rights reserved.
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