SAA7108 Datasheet, PDF (87/202 Pages) NXP Semiconductors – PC-CODEC

Philips Semiconductors
PC-CODEC
Product specification
SAA7108E; SAA7109E
9.5.5
DATA STREAM CODING AND REFERENCE SIGNAL
GENERATION (SUBADDRESSES 84H, 85H AND 93H)
As horizontal and vertical reference signals are logic 1,
active gate signals are generated, which frame the transfer
of the valid output data. Alternatively, the horizontal and
vertical trigger pulses can be generated on the rising
edges of the gates.
Due to the dynamic FIFO behaviour of the complete scaler
path, the output signal timing has no fixed timing
relationship to the real-time input video stream. Thus fixed
propagation delays, in terms of clock cycles, related to the
analog input can not be defined.
The data stream is accompanied by a data qualifier.
Additionally invalid data cycles are marked with code 00H.
If ITU 656 like codes are not required, they can be
suppressed in the output stream.
As a further option, it is possible to provide the scaler with
an external gating signal on pin ITRDY. It is therefore
possible to hold the data output for a certain time and to
get valid output data in bursts of a guaranteed length.
The sketched reference signals and events can be
mapped to the I port output pins IDQ, IGPH, IGPV, IGP0
and IGP1. The polarities of all the outputs can be modified
to enable flexible use. The default polarity for the qualifier
and reference signals is logic 1 (active).
Table 48 shows the relevant and supported SAV and EAV
coding.
Table 48 SAV/EAV codes on the I port
SAV/EAV CODES ON I PORT⁽¹⁾ (HEX)
EVENT DESCRIPTION MSB⁽²⁾ OF SAV/EAV BYTE = 0 MSB⁽²⁾ OF SAV/EAV BYTE = 1 COMMENT
FIELD ID = 0 FIELD ID = 1 FIELD ID = 0 FIELD ID = 1
Next pixel is FIRST pixel of any
0E
active line
Previous pixel was LAST pixel
13
of any active line, but not the
last
Next pixel is FIRST pixel of any
25
V-blanking line
Previous pixel was LAST pixel
38
of the last active line or of any
V-blanking line
No valid data, do not capture
and do not increment pointer
49
80
54
9D
62
AB
7F
B6
00
C7
HREF = active;
VREF = active
DA
HREF = inactive;
VREF = active
EC
HREF = active;
VREF = inactive
F1
HREF = inactive;
VREF = inactive
IDQ pin inactive
Notes
1. The leading byte sequence is: FFH-00H-00H.
2. The MSB of the SAV/EAV code byte is controlled by:
a) Scaler output data: task A ⇒ MSB = CONLH[90H[7]]; task B ⇒ MSB = CONLH[C0H[7]].
b) VBI data slicer output data: DID[5:0] 5DH[5:0] = 3EH ⇒ MSB = 1; DID[5:0] 5DH[5:0] = 3FH ⇒ MSB = 0.
2004 Mar 16
87