SAA7108 Datasheet, PDF (46/202 Pages) NXP Semiconductors – PC-CODEC

Philips Semiconductors
PC-CODEC
Product specification
SAA7108E; SAA7109E
9.1.2.1 Clamping
The clamping control circuit controls the correct clamping
of the analog input signals. A coupling capacitor is used to
store and filter the clamping voltage. An internal digital
clamp comparator generates the information with respect
to clamp-up or clamp-down. The clamping levels for the
two ADC channels are fixed for luminance (60) and
chrominance (128). Clamping time in normal use is set
with the HCL pulse at the back porch of the video signal.
9.1.2.2 Gain control
The gain control circuit receives (via the I²C-bus) the static
gain levels for the two analog amplifiers, or controls one of
these amplifiers automatically via a built-in Automatic Gain
Control (AGC) as part of the Analog Input Control (AICO).
The AGC (automatic gain control for luminance) is used to
amplify a CVBS or Y signal to the required signal
amplitude, which is matched to the ADCs input voltage
range. The AGC active time is the sync bottom of the video
signal.
Signal (white) peak control limits the gain at signal
overshoots. The influence of supply voltage variation
within the specified range is automatically eliminated by
clamping and automatic gain control. The flow charts show
more details of the AGC; see Figs 15 and 16.
TV line
analog line blanking
255
GAIN CLAMP
60
1
HCL
HSY
MGL065
Fig.12 Analog line with clamp (HCL) and gain
range (HSY).
analog input level
+3 dB
0 dB
(1 V (p-p) 18/56 Ω)
−6 dB
maximum
range 9 dB
minimum
controlled
ADC input level
0 dB
MHB325
Fig.13 Automatic gain range.
2004 Mar 16
46