SAA7108 Datasheet, PDF (5/202 Pages) NXP Semiconductors – PC-CODEC

Philips Semiconductors
PC-CODEC
Product specification
SAA7108E; SAA7109E
3 GENERAL DESCRIPTION
The SAA7108E; SAA7109E is a new multi-standard video
decoder and encoder chip, offering high quality video input
and TV output processing as required by PC-99
specifications. It enables hardware manufacturers to
implement versatile video functions on a significantly
reduced printed-circuit board area at very competitive
costs.
Separate pins for supply voltages as well as for I²C-bus
control and boundary scan test have been provided for the
video encoder and decoder sections to ensure both
flexible handling and optimized noise behaviour.
The video encoder is used to encode PC graphics data at
maximum 800 × 600 resolution to PAL (50 Hz) or NTSC
(60 Hz) video signals. A programmable scaler and
interlacer ensures properly sized and flicker-free TV
display as CVBS or S-video output.
Alternatively, the three Digital-to-Analog Converters
(DACs) can output RGB signals together with a TTL
composite sync to feed SCART connectors.
When the scaler/interlacer is bypassed, a second VGA
monitor can be connected to the RGB outputs and
separate H and V-syncs as well, thereby serving as an
auxiliary monitor at maximum 800 × 600 resolution/60 Hz
(PIXCLK < 45 MHz).
The video decoder, a 9-bit video input processor, is a
combination of a 2-channel analog pre-processing circuit
including source selection, anti-aliasing filter and
Analog-to-Digital Converter (ADC), automatic clamp and
gain control, a Clock Generation Circuit (CGC), and a
digital multi-standard decoder (PAL BGHI, PAL M, PAL N,
combination PAL N, NTSC M, NTSC-Japan, NTSC N,
NTSC 4.43 and SECAM).
The decoder includes a brightness, contrast and
saturation control circuit, a multi-standard VBI data slicer
and a 27 MHz VBI data bypass. The pure 3.3 V (5 V
compatible) CMOS circuit SAA7108E; SAA7109E,
consisting of an analog front-end and digital video
decoder, a digital video encoder and analog back-end, is a
highly integrated circuit especially designed for desktop
video applications.
The decoder is based on the principle of line-locked clock
decoding and is able to decode the colour of PAL, SECAM
and NTSC signals into ITU-R BT.601 compatible colour
component values.
The encoder can operate fully independently at its own
variable pixel clock, transporting graphics input data, and
at the line-locked, single crystal-stable video encoding
clock.
As an option, it is possible to slave the video PAL/NTSC
encoding to the video decoder clock with the encoder FIFO
acting as a buffer to decouple the line-locked decoder
clock from the crystal-stable encoder clock.
4 QUICK REFERENCE DATA
SYMBOL
PARAMETER
CONDITIONS
MIN. TYP. MAX. UNIT
V_DDD
V_DDA
T_amb
P_A+D
digital supply voltage
analog supply voltage
ambient temperature
analog and digital power dissipation
note 1
3.0 3.3
3.15 3.3
0
−
−
−
3.6 V
3.45 V
70
°C
1.4 W
Note
1. Power dissipation is extremely dependent on programming and selected application.
5 ORDERING INFORMATION
TYPE
NUMBER
SAA7108E
SAA7109E
NAME
BGA156
PACKAGE
DESCRIPTION
plastic ball grid array package; 156 balls; body 15 × 15 × 1.15 mm
VERSION
SOT472-1
2004 Mar 16
5