SAA7108 Datasheet, PDF (108/202 Pages) NXP Semiconductors – PC-CODEC

Philips Semiconductors
PC-CODEC
Product specification
SAA7108E; SAA7109E
SYMBOL
PARAMETER
CONDITIONS
MIN.
9-bit analog-to-digital converters
B
analog bandwidth
at −3 dB
−
φ_diff
differential phase
−
(amplifier plus anti-alias
filter bypassed)
G_diff
differential gain (amplifier
−
plus anti-alias filter
bypassed)
f_clk(ADC)
DLE_dc(d)
ADC clock frequency
DC differential linearity
error
12.8
−
ILE_dc(i)
DC integral linearity error
−
Digital inputs
V_{IL(SDAd,SCLd)} LOW-level input voltage
pins SDAd and SCLd
−0.5
V_{IH(SDAd,SCLd)} HIGH-level input voltage
pins SDAd and SCLd
0.7V_DDD
V_IL(XTALId)
LOW-level CMOS input
voltage pin XTALId
−0.3
V_IH(XTALId)
HIGH-level CMOS input
2.0
voltage pin XTALId
V_IL(n)
LOW-level input voltage all
other inputs
−0.3
V_IH(n)
HIGH-level input voltage
2.0
all other inputs
I_LI
input leakage current
−
I_LI/O
I/O leakage current
−
C_i
input capacitance
I/O at high-impedance
−
Digital outputs; note 1
V_OL(SDAd)
LOW-level output voltage SDAd at 3 mA sink current −
pin SDAd
V_OL(clk)
LOW-level output voltage
for clocks
−0.5
V_OH(clk)
HIGH-level output voltage
2.4
for clocks
V_OL
LOW-level output voltage
0
all other digital outputs
V_OH
HIGH-level output voltage
2.4
all other digital outputs
Clock output timing (LLC and LLC2); note 2
C_L(LLC)
output load capacitance
15
T_cy
cycle time
pin LLC
35
pin LLC2
70
TYP.
7
2
2
−
0.7
1
−
−
−
−
−
−
−
−
−
−
−
−
−
−
−
−
−
MAX. UNIT
−
MHz
−
deg
−
%
14.3
MHz
−
LSB
−
LSB
+0.3V_DDD V
V_DDD + 0.5 V
+0.8
V
V_DDD + 0.3 V
+0.8
V
5.5
V
1
µA
10
µA
8
pF
0.4
V
+0.6
V
V_DDD + 0.5 V
0.4
V
V_DDD + 0.5 V
50
pF
39
ns
78
ns
2004 Mar 16
108