TDA8260TW Datasheet, PDF (8/23 Pages) NXP Semiconductors – Satellite Zero-IF QPSK/8PSK downconverter with PLL synthesizer

Philips Semiconductors
Satellite Zero-IF QPSK/8PSK
downconverter with PLL synthesizer
Product specification
TDA8260TW
PROGRAMMABLE ADDRESSES
The programmable address bits MA1 and MA0 offer the
possibility of having up to four TDA8260TW devices in the
same system. The relationship between the voltage
applied to pin AS and the value of bits MA1 and MA0 is
given in Table 3.
Table 3 I²C-bus address selection
V_AS
0 to 0.1V_CC
open-circuit
0.4V_CC to 0.6V_CC
0.9V_CC to V_CC
MA1
0
0
1
1
MA0
0
1
0
1
PROGRAMMABLE MAIN DIVIDER RATIO
Program bytes PD1 and PD2 contain the fifteen bits
N14 to N0 that set the main divider ratio. The ratio
N = N14 × 2¹⁴ + N13 × 2¹³ +...+ N1 × 2 + N0.
OPERATING AND TEST MODES
The mode of operation is set using bits T2, T1 and T0 in
control byte CD1; see Table 4.
Table 4 Mode selection
T2 T1 T0
MODE
XTOUT
0 0 0 normal operation
OFF
0
0
1 POR state = CP sink⁽¹⁾ f_XTAL
0
1
0 ¹/₂ × f_DIV
1_{/2 × fDIV}
0 1 1 CP sink
f_XTAL
1 0 0 normal operation
f_XTAL
1
0
1 2 × f_ref
2 × f_ref
1 1 0 CP OFF
f_XTAL
1 1 1 CP source
f_XTAL
Note
1. Status at power-on: the tuning voltage output is
released and pin VT is in the high-impedance state.
REFERENCE DIVIDER
Five reference divider ratios allow the adjustment of the
comparison frequency to different values depending on
the compromise that has to be found between step size
and phase noise. The reference divider ratios and the
corresponding comparison frequencies are programmed
using bits R2, R1 and R0; see Table 5.
Table 5 Reference divider ratio
R2 R1 R0 DIVIDER RATIO
COMPARISON
FREQUENCY
000
2
2 MHz
001
4
1 MHz
010
8
500 kHz
011
not allowed
100
not allowed
101
16
250 kHz
110
not allowed
111
32
125 kHz
CHARGE PUMP CURRENT
Four values of charge pump current can be chosen using
bits C1 and C0; see Table 6.
Table 6 Charge pump current
TYPICAL CHARGE PUMP
C1
C0
CURRENT ABSOLUTE VALUES
(µA)
0
0
420
0
1
900
1
0
1 360
1
1
2 320
2004 Sep 03
8