TDA8260TW Datasheet, PDF (6/23 Pages) NXP Semiconductors – Satellite Zero-IF QPSK/8PSK downconverter with PLL synthesizer

Philips Semiconductors
Satellite Zero-IF QPSK/8PSK
downconverter with PLL synthesizer
Product specification
TDA8260TW
handbook, halfpage
XT1 1
38 XTOUT
XT2 2
37 SDA
VCC(PLL) 3
PLLGND 4
36 SCL
35 AS
AGCIN 5
34 CP
BIASN 6
33 VT
RFGND1 7
32 BVS
VCC(RF) 8
RFA 9
31 VCC(VCO)
30 TKA
RFB 10
29 TKB
TDA8260TW
RFGND2 11
28 VCOGND
LP1 12
27 CAP1
LP2 13
26 CAP2
QOUT 14
25 IOUT
BBGND1 15
24 BBGND2
QBBIN 16
23 IBBIN
VCC(BB) 17
QBBOUT 18
22 n.c.
21 IBBOUT
QIN 19
20 IIN
MGU791
Fig.2 Pin configuration.
FUNCTIONAL DESCRIPTION
The TDA8260TW contains the core of the RF analog part
of a digital satellite receiver. The signal coming from the
Low Noise Block (LNB) is coupled through a Low Noise
Amplifier (LNA) to the RF inputs. The internal circuitry
performs the Zero-IF quadrature frequency conversion
and the two in-phase (IBBOUT) and quadrature
(QBBOUT) output signals can be used directly to feed a
Satellite Demodulator and Decoder circuit (SDD).
The TDA8260TW has a gain-controlled amplifier in the
converter circuit. The gain is controlled by the AGCIN input
from the SDD.
An external VCO tank circuit is connected between pins
TKA and TKB. The main elements of the external tank
circuit are an SMD coil and a varactor diode. The tuning
voltage of 0 to 30 V covers the whole frequency range
from 237.5 to 543.75 MHz. The internal loop controls a
fully integrated VCO to cover the range 950 to 2175 MHz.
The VCO provides both in-phase and quadrature signals
to drive the two mixers.
Except for the 4 MHz crystal and the loop filter, all circuit
components necessary to control the varactor-tuned
oscillator are integrated in the TDA8260TW. The tuning
circuit includes a fast phase detector with a high
comparison frequency in order to achieve the lowest
possible level of phase noise in the local oscillator.
The f_DIV output of the15-bit programmable divider passes
through the fast phase comparator where it is compared in
both phase and frequency with the comparison frequency
(f_COMP). The frequency f_COMP is derived from the signal
present at the XT1/XT2 pins (f_XTAL) divided-down by the
reference divider. The buffered XTOUT signal can drive
the crystal frequency input of the SDD, thereby saving a
crystal in the application.
The output of the phase comparator drives the charge
pump and loop amplifier section. The loop amplifier
includes a high voltage transistor to handle the 30 V tuning
voltage at pin VT, this drives a variable capacitance diode
in the external circuit of the voltage controlled oscillator.
Pin CP is the output of the charge pump. The loop filter is
connected between pins CP and VT and the post-filter
section is connected between pin VT and the variable
capacitance diode.
For test and alignment purposes, it is possible to release
the tuning voltage output and apply an external voltage to
pin VT, also to select the charge pump function to sink
current, source current or to be switched off.
2004 Sep 03
6