TDA4887PS Datasheet, PDF (8/68 Pages) NXP Semiconductors – 160 MHz bus-controlled monitor video preamplifier

Philips Semiconductors
160 MHz bus-controlled monitor video
preamplifier
Product specification
TDA4887PS
7 FUNCTIONAL DESCRIPTION
Refer also to block diagram (Fig.1) and definitions of levels
and signals (Chapter 10).
7.1 Signal input stage
The RGB input signals are capacitively coupled into the
TDA4887PS from a low-ohmic source (75 Ω
recommended) and actively clamped to the internal
reference black level during signal black level. The signal
amplitude is 0.7V_i(b-w) and should not exceed 1 V. The
high-ohmic input impedance of the TDA4887PS allows the
coupling capacitor to be relatively small (10 nF
recommended). The coupling capacitor also functions as a
storage capacitor between clamping pulses. Very small
input currents will discharge the coupling capacitor
resulting in black output signals for missing input clamping
pulses.
Composite signals will not disturb normal operation
because a clipping circuit cuts all signal parts below black
level.
A fast signal blanking circuit included in the input stage is
driven by several blanking pulses (see Section 7.6) and
control bit DISV = 1. During the off condition the internal
reference black level is inserted instead of the input
signals.
7.2 Electronic potentiometer stages
7.2.1 CONTRAST CONTROL
The contrast control is driven by an 8-bit DAC via the
I²C-bus. The input signals related to the internal reference
black level can be adjusted simultaneously by contrast
control with a control range of 32 dB (typical). The nominal
setting is for maximum contrast.
7.2.2 BRIGHTNESS CONTROL
7.2.2.1 Brightness control with grey scale tracking
The brightness control is driven by an 8-bit DAC via the
I²C-bus; brightness control with grey scale tracking is
selected when control bit BRI = 0.
With brightness control, the video black level is shifted in
relation to the reference black level simultaneously for all
three channels. With a negative setting (up to 10% of the
maximum signal amplitude) dark signal parts will be lost in
ultra black; for positive settings (up to 33% of the maximum
signal amplitude) the background will alter from black to
grey. At nominal brightness setting (40H) there is no shift.
The brightness setting is also valid for OSD signals. During
blanking and output clamping the video black level will be
blanked to the reference black level (brightness blanking).
The brightness information is inserted before the gain
potentiometers, background colour temperature will not
change with brightness setting (grey scale tracking).
7.2.2.2 Brightness control without grey scale tracking
Brightness control without grey scale tracking is selected
when control bit BRI = 1.
The brightness information will be mixed with the DAC
outputs for external black level restoration (FPOL = 1,
AC-coupled cathodes) or internal feedback reference
voltages (FPOL = 0, DC-coupled cathodes). This allows a
simple bus-controlled brightness setting without grey scale
tracking. With AC-coupled cathodes this is equivalent to
brightness control via grid G1.
7.2.3 GAIN CONTROL AND GREY SCALE TRACKING
The gain control is driven by an 8-bit DAC via the I²C-bus.
Gain control is used for white point adjustment (correction
for different voltage-to-light amplification of the three
colour channels) and therefore individually for R, G and B.
The video signals related to the reference black level can
be gain-controlled within a range of 14 dB (typical). This
range is large enough to accommodate the maximum
output amplitude for different applications. The nominal
setting is maximum gain. The gain setting is also valid for
OSD signals and brightness shift (BRI = 0), therefore the
complete ‘grey scale’ is effected by gain control.
7.3 Output stage
In the output stage the nominal input signal will be
amplified to provide a 4.6 V (typical) output colour signal at
maximum contrast and maximum gain settings. Reference
or pedestal black levels are adjusted by output clamping.
In order to achieve fast rise and fall times of the output
signals with minimum crosstalk between the channels,
each signal stage has its own supply voltage pin.
2001 Oct 19
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