TDA4887PS Datasheet, PDF (34/68 Pages) NXP Semiconductors – 160 MHz bus-controlled monitor video preamplifier

Philips Semiconductors
160 MHz bus-controlled monitor video
preamplifier
Product specification
TDA4887PS
Table 4 Subaddress and data byte format
SUBADDRESS⁽¹⁾
FUNCTION
DIRECT
MODE
BUFFERED
MODE
D7⁽⁴⁾
D6⁽⁴⁾
Control register
00H
80H
X⁽⁵⁾ BRI
Brightness control 01H
81H
A17 A16
Contrast control
02H
82H
A27 A26
OSD contrast
control
03H
83H
X⁽⁵⁾ X⁽⁵⁾
Gain control
channel 1
04H
84H
A47 A46
Gain control
channel 2
05H
85H
A57 A56
Gain control
channel 3
06H
86H
A67 A66
Black level
07H
reference channel 1
87H
A77 A76
Black level
08H
reference channel 2
88H
A87 A86
Black level
09H
reference channel 3
89H
A97 A96
Black level for
AC coupling
0AH
8AH
X⁽⁵⁾ X⁽⁵⁾
Depth of pedestal
0BH
blanking
8BH
X⁽⁵⁾ X⁽⁵⁾
D5⁽⁴⁾
X⁽⁵⁾
A15
A25
X⁽⁵⁾
A45
A55
A65
A75
A85
A95
X⁽⁵⁾
X⁽⁵⁾
DATA BYTE⁽²⁾
D4⁽⁴⁾ D3⁽⁴⁾ D2⁽⁴⁾ D1⁽⁴⁾
X⁽⁵⁾ FPOL DISV DISO
A14 A13 A12 A11
A24 A23 A22 A21
X⁽⁵⁾ A33 A32 A31
A44 A43 A42 A41
A54 A53 A52 A51
A64 A63 A62 A61
A74 A73 A72 A71
A84 A83 A82 A81
A94 A93 A92 A91
X⁽⁵⁾ X⁽⁵⁾ AA2 AA1
X⁽⁵⁾ X⁽⁵⁾ X⁽⁵⁾ AB1
D0⁽⁴⁾
X⁽⁵⁾
A10
A20
A30
A40
A50
A60
A70
A80
A90
AA0
AB0
NOMINAL
VALUE⁽³⁾
08H
40H
FFH
0FH
FFH
FFH
FFH
−
−
−
−
00
Notes
1. See Table 3 (Subaddress byte format).
2. The least significant bit (LSB) of an analog alignment register is defined as AX0 (data bit D0).
3. Under certain conditions the nominal values lead to nominal colour signals, etc. (see notes 1 and 3 of
Chapter “Characteristics” and Figs 4 to 6).
After power-up and after internal Power-on reset of the I²C-bus the registers are set to the following values:
a) Control bit FPOL to logic 1.
b) Control bits DISV, DISO and BRI to logic 0.
c) All other alignment registers to logic 0 (minimum value for control registers).
4. Data bit.
5. X means don’t care but the bits are preferably set to logic 0 for software compatibility with other video ICs that have
the same slave address.
2001 Oct 19
34