TDA4887PS Datasheet, PDF (13/68 Pages) NXP Semiconductors – 160 MHz bus-controlled monitor video preamplifier

Philips Semiconductors
160 MHz bus-controlled monitor video
preamplifier
Product specification
TDA4887PS
10 CHARACTERISTICS
All voltages and currents are measured in a dedicated test circuit (see Fig.17) optimized for best high frequency
performance; all voltages are measured with respect to GND (pins 9 and 14); V_P = V_P1,2,3 = 8 V (pins 7, 21, 18 and 15);
T_amb = 25 °C; nominal input signals [0.7 V (p-p) at pins 6, 8 and 10]; maximum colour signals at signal outputs (pins 22,
19 and 16); reference black level (V_bl(ref)) approximately 0.7 V; nominal setting for brightness; maximum settings for
OSD contrast, contrast and gain; no subcontrast, modulation of contrast or limiting (V_LIM ≥ 5 V); no OSD fast blanking
(pin 1 connected to ground); notes 1 to 3; unless otherwise specified.
SYMBOL
PARAMETER
CONDITIONS
MIN. TYP. MAX. UNIT
Supplies
V_P
V_P(SO)
I_P
V_P(n)
I_P(n)
supply voltage (pin 7)
supply voltage threshold at note 1
pin 7 at which signal outputs
are switched off
supply current (pin 7)
note 4
supply voltage; channels 1,
2 and 3 (pins 21, 18 and 15)
supply current; channels 1,
2 and 3 (pins 21, 18 and 15)
pins 22, 19 and 16
open-circuit;
V_bl(n)(ref) = 0.7 V;
notes 4 and 5
7.6
8.0 8.8
V
6.8
7.0 7.2
V
−
25 30
mA
7.6
8.0 8.8
V
−
20 25
mA
Input clamping and vertical blanking input, validation of buffered I²C-bus data (CLI; pin 5)
V_CLI
input clamping and vertical notes 6 and 7
blanking input signal
no vertical blanking,
−0.1
−
no input clamping
vertical blanking,
no input clamping
1.6
−
input clamping,
3.5
−
no vertical blanking
I_CLI
input current
V_CLI = 1 V
−
−0.2
pin 5 connected to ground; −80
−45
note 8
V_CLI = −0.1 V; note 8
−250
−135
t_r/f5
rise/fall time for input
note 6; see Fig.7
−
−
clamping pulse; disable for
vertical blanking
t_W(CLI)
width of input clamping
pulse
200
−
t_{W(I2C)(valid)}
width of vertical blanking leading and trailing edge 10
−
pulse for validation of
threshold V_CLI = 1.4 V;
buffered I²C-bus data
note 7
t_{d(I2C)(valid)}
delay between leading edge I²C-bus buffered mode
−
−
of vertical blanking pulse transmission completed;
and validation of buffered
I²C-bus data
leading edge threshold
V_CLI = 1.4 V; note 7;
see Fig.7
+1.2
2.6
V_P
−
−30
−100
75
−
−
2
V
V
V
µA
µA
µA
ns/V
ns
µs
µs
2001 Oct 19
13