SA1638 Datasheet, PDF (8/26 Pages) NXP Semiconductors – Low voltage IF I/Q transceiver

Philips Semiconductors
Low voltage IF I/Q transceiver
Product specification
SA1638
AC ELECTRICAL CHARACTERISTICS (Continued)
SYMBOL
PARAMETER
TEST CONDITIONS
LIMITS
MIN
–3σ
TYP
+3σ
UNITS
MAX
IF Synthesizer (cont.)
DI_CP
I_CP
∆I_{CP_M}
|I_{CP_L}|
t_ON
Relative output current variation⁴
Output current matching⁵
Output leakage current
Turn ON time
I_REF =31.2µA
I_REF =31.2µA,
V_CP = V_CCCP/2
V_CP = 0.3V to V_CCCP-0.3V
POnPLL = HI, to full charge
pump current
0.1
1.3
2.5
±10
%
±12
%
-0.02 0.1 0.22 ±15
nA
15
µs
POnPLL = LO, to I_CCCP,
t_OFF Turn OFF time⁶
I_CCDIG <5% of operational
15
µs
supply current
Serial Interface⁷
f_CLOCK
t_SU
Clock frequency
Set-up time: DATA to CLOCK,
CLOCK to STROBE
10
MHz
30
ns
t_H
Hold time: CLOCK to DATA
30
ns
Pulse width: CLOCK
t_W
Pulse width: STROBE
30
ns
30
NOTES:
1. Parameter measured relative to modulation sideband amplitude.
2. After programming the DC offset register for minimum offset. DCRES = 562kΩ.
3. The turn on time relates only to the power up time of the circuit. The settling time of the integrated baseband filters has to be added (for
GSM–mode = 8µs with filter bandwidth setting resistor = 36kΩ).
4. The relative output current variation is defined thus:
DI_OUT
I_OUT
+
2
@
(I₂
|(I₂
*
)
I₁)
I₁)|
;
with
V₁
=
0.3V,
V₂
=
V_CCCP
–
0.3V
(see
Figure
3).
5. The output current matching is measured when both (positive current and negative current) sections of the output charge pumps are on.
6. As soon as P_ONPLL is set to LO, the phase detector is reset and no charge pumps pulses are generated.
7. Guaranteed by design.
ƪ ǒ Ǔƫ 8. NF =
20 log
E_no
Ǹ_4kTR
* VG
where, E_no is the output noise voltage measured in a 1Hz bandwidth, R = 1200Ω, VG = gain in dB.
9. Minimium frequency is guaranteed by design.
CURRENT
I₂
I₁
VOLTAGE
address bits and 1 subaddress bit. Figure 2 shows the timing
diagram of the serial input. When the STROBE = L, the clock driver
is enabled and on the positive edges of the CLOCK the signal on
DATA input is clocked into a shift register. When the STROBE = H,
the clock is disabled and the data in the shift register remains stable.
Depending on the value of the subaddress bit the data is latched
into different working registers. Table 3 shows the contents of each
word.
V₁
I₂
V₂
Default States
Upon power up (V_CCDIG is applied) a reset signal is generated,
which sets all registers to a default state. The logic level at the
STROBE pin should be low during power up to guarantee a proper
reset. These default states are shown in Table 3.
I₁
SR00526
Figure 3. Relative Output Current Variation
FUNCTIONAL DESCRIPTION
Serial Programming Input
The serial input is a 3-wire input (CLOCK, STROBE, DATA) to
program the counter ratios, charge pump current, status- and
DC-offset register, mode select and test register. The programming
data is structured into two 21-bit words; each word includes 4 chip
Reference Divider
The reference divider can be programmed to four different division
ratios (:13, :26, :39, :52), see registers r0, r1; default setting: divide
by 13.
Main Divider
The external VCO signal, applied to the LO_IN and LO_INX inputs, is
divided by two and then fed to the main divider (:N). The main
divider is a programmable 9 bit divider, the minimum division ratio is
1997 Sept 03
8