SA1638 Datasheet, PDF (10/26 Pages) NXP Semiconductors – Low voltage IF I/Q transceiver

Philips Semiconductors
Low voltage IF I/Q transceiver
Product specification
SA1638
The overall filter response in the receive section is the sum of the
filter responses of the passive RC low-pass filter and the active
gyrator filter.
Power Down Modes
There are 4 power-on pins in the SA1638: P_ON, P_ONRx, PDTx,
P_ONPLL.
P_ON = H powers up both voltage regulators V_REG1 and V_REG2. P_ON
should be set to L, if these internal voltage regulators are not to be
used.
P_ONRx = H powers up the receiver part.
PDTx = L powers up the transmitter part.
P_ONPLL = H powers up the synthesizer part. As it also powers up
the first divide by 2 stage for generating the 0/90 degree phase
shifted signals for the transmit and receive mixers, it also has to be
set H if either the transmit part or the receive part is used. P_ONPLL
= L powers down the dividers, resets the phase detector and
disconnects the current setting pin I_REF. In P_ONPLL = L mode, the
values in the serial input registers are still kept and the part still can
be reprogrammed as long as V_CCDIG is present.
Table 3. Definition of SA1638 Serial Registers
First data word: (shown with default values)
Address SA1638
Sub
Adr
N-Divider
Ref ÷ Reg Charge-Pump Reg Test
MSB
LSB
a0 a1 a2 a3 sa n0 n1 n2 n3 n4 n5 n6 n7 n8 r0 r1 c0 c1 c2 x0 x1
111001100100000011100
Address: 4 bits, a0...a3, fixed to 1110
Sub:Address: 1 bit, sa, fixed to 0 for first data word
N-Divider: 9 bits, n0...n8, values 64 (00100 0000) to 511 (111111111) allowed for IF-choice, default 400
Reference Divider Register: 2 bits, r0...r1, 00 = ÷13, 01 = ÷26, 10 = ÷39, 11 = ÷52. Default: 00
Charge-Pump Register: 3 bits, c0...c2, Binary current setting factor for charge pumps, values 000 = minimum current to 111 =
maximum current, default maximum charge pump current
Test Register: 2 bits, x0...x1, default 00, see Functional Description
Second data word: (shown with default values)
Address SA1638
Sub Status
Adr
Reg
DC Offset Register
Q-Channel
I-Channel
Mode Select Register
MSB
LSB
a0 a1 a2 a3 sa s0 s1 q0 q1 q2 q3 i0 i1 i2 i3 t0 t1 t2 t3 t4 t5
111011100000000000000
Address: 4 bits, a0...a3, fixed to 1110
Sub:Address: 1 bit, sa, fixed to 1 for second data word
Status Register:
DC Offset Register:
2 bits, s0 sets pin A_OUT; s1 sets pin B_OUT, see Functional Description
4 bits per channel, i0...i3 and q0...q3, no correction as default
i0 and q0 switches offset polarity, 0 to lower voltage, 1 to higher voltage
il...i3 and q1...q3, 000 no correction to 111 max. correction enabled
Mode Select Register: 6 bits, t0...t5, 000000 = normal GSM-Operation as default, see Functional Description
1997 Sept 03
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