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74HC7404 Datasheet, PDF (8/28 Pages) NXP Semiconductors – 5-Bit x 64-word FIFO register; 3-state | |||
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Philips Semiconductors
5-Bit x 64-word FIFO register; 3-state
Product speciï¬cation
74HC/HCT7404
Tamb °C
TEST CONDITION
SYMBOL PARAMETER
+25
â40 to +85 â40 to +125 UNIT VCC
MIN TYP MAX MIN MAX MIN MAX
(V)
WAVEFORMS
tW
DIR pulse width 10 41 130 8
165 8
195 ns 2.0
Fig.8
HIGH
5
15 26 4
33 4
39 ns 4.5
4
12 22 3
28 3
33 ns 6.0
tW
DOR pulse
14 52 160 12 200 12 240 ns 2.0
Fig.11
width HIGH
7
19 32 6
40 6
48 ns 4.5
6
15 27 5
34 5
41 ns 6.0
tW
MR pulse
120 39 â
150 â
180 â
ns 2.0
Fig.9
width LOW
24 14 â
30 â
36 â
ns 4.5
20 11 â
26 â
31 â
ns 6.0
trem
removal time 80 24 â
100 â
120 â
ns 2.0
Fig.16
MR to SI
16 8
â
20 â
24 â
ns 4.5
14 7
â
17 â
20 â
ns 6.0
tsu
set-up time
â8 â36 â
â6 â
â6 â
ns 2.0
Fig.14
Dn to SI
â4 â13 â
â3 â
â3 â
ns 4.5
â3 â10 â
â3 â
â3 â
ns 6.0
th
hold time
135 44 â
170 â
205 â
ns 2.0
Fig.14
Dn to SI
27 16 â
34 â
41 â
ns 4.5
23 13 â
29 â
35 â
ns 6.0
fmax
maximum clock 3.6 9.9 â
2.8 â
2.4 â
MHz 2.0
Fig.12 and
pulse frequency 18 30 â
14 â
12 â
MHz 4.5
Fig.13
SI, SO burst 21 36 â
16 â
14 â
MHz 6.0
mode
fmax
maximum clock 3.6 9.9 â
2.8 â
2.4 â
MHz 2.0
Fig.7 and
pulse frequency 18 30 â
14 â
12 â
MHz 4.5
Fig.10
SI, SO using 21 36 â
16 â
14 â
MHz 6.0
ï¬ags
fmax
maximum clock â
7.6 â
â
â
â
â
MHz 2.0
Fig.7 and
pulse frequency â
23 â
â
â
â
â
MHz 4.5
Fig.10
SI, SO
â
27 â
â
â
â
â
MHz 6.0
cascaded
September 1993
8
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