74HC7404 Datasheet, PDF (28/28 Pages) NXP Semiconductors – 5-Bit x 64-word FIFO register; 3-state

Philips Semiconductors
5-Bit x 64-word FIFO register; 3-state
Product specification
74HC/HCT7404
Sequence 2 (FIFO_B runs full)
After the MR pulse, a series of 64 SI
pulses are applied. When 64 words
are shifted in, DIR_B remains LOW due
to FIFO_B being full (5). DOR_A goes
LOW due to FIFO_A being empty.
Sequence 3 (FIFO_A runs full)
When 65 words are shifted in, DOR_A
remains HIGH due to valid data
remaining at the output of FIFO_A. Q_nA
remains HIGH, being the polarity of
the 65th data word (6). After the 128th
SI pulse, DIR remains LOW and both
FIFOs are full (7). Additional pulses
have no effect.
Sequence 4 (both FIFOs full,
starting SHIFT-OUT process)
SI_A is held HIGH and two SO_B pulses
are applied (8). These pulses shift out
two words and thus allow two empty
locations to bubble-up to the input
stage of FIFO_B, and proceed to FIFO_A
(9). When the first empty location
arrives at the input of FIFO_A, a DIR_A
pulse is generated (10) and a new
word is shifted into FIFO_A. SI_A is
made LOW and now the second
empty location reaches the input
stage of FIFO_A, after which DIR_A
remains HIGH (11).
Sequence 5 (FIFO_A runs empty)
At the start of sequence 5 FIFO_A
contains 63 valid words due to two
words being shifted out and one word
being shifted in, in sequence 4. An
additional series of SO_B pulses are
applied. After 63 SO_B pulses, all
words from FIFO_A are shifted into
FIFO_B. DOR_A remains LOW (12).
Sequence 6 (FIFO_B runs empty)
After the next SO_B pulse, DIR_B
remains HIGH due to the input stage
of FIFO_B being empty. After another
63 SO_B pulses, DOR_B remains LOW
due to both FIFOs being empty (14).
Additional SO_B pulses have no effect.
The last word remains available at the
output Q_n.
PACKAGE OUTLINES
See “74HC/HCT/HCU/HCMOS Logic
Package Outlines”.
September 1993
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