74HC7404 Datasheet, PDF(23/28 Page) NXP Semiconductors – 5-Bit x 64-word FIFO register; 3-state

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74HC7404 Datasheet, PDF (23/28 Pages) NXP Semiconductors – 5-Bit x 64-word FIFO register; 3-state

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Philips Semiconductors

5-Bit x 64-word FIFO register; 3-state

Product speciï¬cation

74HC/HCT7404

handbook, full pagewidth

composite

DIR

Qn 5

DIR DOR

7404

DIR DOR

7404

Qn 5

MGA685

composite

DOR

Fig.20 Expanded FIFO for increased word length.

Note to Fig.20

This circuit is only required if the SI input is constantly held HIGH, when the FIFO is empty and the automatic shift-in

cycles are started or if SO output is constantly held HIGH, when the FIFO is full and the automatic shift-out cycles are

started (see Fig.8 and Fig.10).

Expanded format

Figure 21 shows two cascaded FIFOs providing a capacity of 128 words x 5 bits. Figure 22 shows the signals on the

nodes of both FIFOs after the application of a SI pulse, when both FIFOs are initially empty. After a ripple through delay,

data arrives at the output of FIFOA. Due to SOA being HIGH, a DORA pulse is generated. The requirements of SIB and

DnB are satisfied by the DORA pulse width and the timing between the rising edge of DORA and QnA. After a second ripple

through delay, data arrives at the output of FIFOB.

Figure 23 shows the signals on the nodes of both FIFOs after the application of a SOB pulse, when both FIFOs are initially

full. After a bubble-up delay a DIRB pulse is generated, which acts as a SOA pulse for FIFOA. One word is transferred

from the output of FIFOA to the input of FIFOB. The requirements of the SOA pulse for FIFOA is satisfied by the pulse

width of DORB. After a second bubble-up delay an empty space arrives at DnA, at which time DIRA goes HIGH.

Figure 24 shows the waveforms at all external nodes of both FIFOs during a complete shift-in and shift-out sequence.

September 1993

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