74HC7404 Datasheet, PDF (17/28 Pages) NXP Semiconductors – 5-Bit x 64-word FIFO register; 3-state

Philips Semiconductors
5-Bit x 64-word FIFO register; 3-state
Shift-in operation; high-speed burst mode
Product specification
74HC/HCT7404
handbook, full pagewidth
SI INPUT
Dn INPUT
DIR OUTPUT
1/f _max
tW
VM ⁽¹⁾
MGA662
(1) HC : V_M = 50%; V_I = GND to V_CC.
HCT : V_M = 1.3 V; V_I = GND to 3 V.
Fig.12 Waveforms showing SI minimum pulse width and maximum pulse frequency, in high-speed shift-in burst
mode.
Note to Fig.12
In the high-speed mode, the burst-in rate is determined by the minimum shift-in HIGH and shift-in LOW specifications.
The DIR status flag is a don't care condition, and a shift-in pulse can be applied regardless of the flag. A SI pulse which
would overflow the storage capacity of the FIFO is ignored.
September 1993
17