TDA8798 Datasheet, PDF (7/24 Pages) NXP Semiconductors – Dual 8-bit, 100 Msps A/D converter with DPGA

Philips Semiconductors
Dual 8-bit, 100 Msps A/D converter with
DPGA
Objective specification
TDA8798
FUNCTIONAL DESCRIPTION
The TDA8798 comprises two independent fully differential
signal chains each having a DPGA and a high-speed ADC.
A serial interface allows the gain of each DPGA to be
controlled independently. To improve signal conditions, an
AC-coupled external filter can be connected between a
DPGA and ADC. The TDA8798 can be used as a dual 8-bit
ADC without DPGA functionality, using less power.
Digitally Programmable Gain Amplifier (DPGA)
The gain of the differential DPGA is programmable from
0 to 34 dBV in 63 equal steps by a 6-bit word output in
parallel from a gain control register in the SI. For all gain
settings, the DPGA signal bandwidth exceeds 30 MHz.
The settling time between gain changes can be adjusted
by an external decoupling capacitor connected to
DPGAC1 (pin 14) and/or DPGAC2 (pin 3). The analog
input signals can be either AC or DC coupled. When used
only as a dual 8-bit ADC, both DPGAs can be disabled to
reduce power consumption.
Analog-to-Digital Converter (ADC)
The 8-bit ADC converts the differential analog input signal
into a binary output format at a maximum conversion rate
of 100 Msps. All digital input and output signals are
TTL/CMOS compatible.
The ADC clock signal can be from either a differential or a
single-ended source; when single-ended, the unused
clock input pin should be decoupled externally. The analog
input to the ADC is AC coupled.
When used only as a dual ADC, the ADC can be externally
biased by regulator output V_oref1 (pin 19) and/or
V_oref2 (pin 62) using series resistors of, for example, 50 Ω,
connected to the ADC buffer inputs providing a lower input
impedance. This requires V_oref1 and/or V_oref2 to be
decoupled to ground by a 10 nF capacitor.
V_ref1 (pin 13) and/or V_ref2 (pin 4) provide a voltage
corresponding to the bias of the ADC which can be used
as a reference output to an external control circuit.
Alternatively, an external control voltage can be applied to
these pins to adjust the full-scale range of the ADC.
Serial Interface (SI)
The SI allows the gain of each DPGA to be controlled
independently using either a parallel load mode or a
count-up/count-down mode. The gain control mode is
selected by the state of SMODE. The operation of DPGA
gain control is shown in Timing diagram, (see Fig.4).
Parallel load mode
This mode loads gain control data serially into a decoder
in the SI. Each of the six bits are loaded on the rising edge
of SCLK. After the load has completed, SEN goes inactive,
loading the data in parallel to a gain control register in the
SI, changing the gain of the DPGA.
Count-up/count-down mode
Count-up/count-down mode is selected when SMODE is
in the opposite state to parallel load mode. This mode
either increments or decrements the SI gain control
register in one-bit steps when SEN and SCLK are both
active; the state of SDATA determines the count direction
(up or down). This allows the gain of the DPGA to be
changed asynchronously and intermittently.
ADC digital outputs
Digital noise on the internal supply lines increases when
the V_DDO voltage increases, affecting the crosstalk
between channels. This effect can be reduced by making
SR (pin 52) HIGH, changing the slew-rate of the ADC
digital outputs.
1999 Sep 16
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