TDA8798 Datasheet, PDF (14/24 Pages) NXP Semiconductors – Dual 8-bit, 100 Msps A/D converter with DPGA

Philips Semiconductors
Dual 8-bit, 100 Msps A/D converter with
DPGA
Objective specification
TDA8798
SYMBOL
PARAMETER
CONDITIONS
MIN.
TYP.
MAX. UNIT
COMMON MODE REFERENCE OUTPUTS (V_OREF1 AND V_OREF2)
V_o(ref)
R_o(ref)
I_o(ref)
reference output voltage
−
reference output resistance at V_o(cm)(ref)
−
reference maximum output
current
at V_o(cm)(ref) − 0.2 V −
C_o(ref)
reference output capacitance
−
Serial Interface
V_DDA − 0.42 V −
V
400
−
Ω
170
−
µA
−
3
pF
DIGITAL INPUTS (SEN1, SEN2, SCLK, SDATA AND SMODE)
V_IL
LOW-level input voltage
V_IH
HIGH-level input voltage
I_IH
HIGH-level input current
I_IL
LOW-level input current
GAIN CONTROL DATA TIMING (see Fig.4)
f_SCLK(max)
t_W(SCLKH)
t_W(SCLKL)
t_su(SEN-SCLK)
t_h(SEN-SCLK)
t_{su(SDATA-SCLK)}
t_{h(SMODE-SCLK)}
t_h(SMODE-SEN)
t_d(SEN-Q)
maximum clock frequency
clock pulse width HIGH
clock pulse width LOW
SEN to SCLK set-up time
SEN to SCLK hold time
SDATA to SCLK set-up time
SMODE to SCLK hold time
SMODE to SEN hold time
delay SEN rising edge to
change gain control register
value
t_d(SCLK-Q)
delay SCLK rising edge to
change gain control register
value
0
−
2.0
−
−5
0
−5
0
5
−
20
−
20
−
5
−
5
−
5
−
5
−
5
−
−
−
−
−
0.8 V
V_DDD V
+5 µA
+5 µA
−
MHz
−
ns
−
ns
−
ns
−
ns
−
ns
−
ns
−
ns
5
ns
5
ns
Note
1. Single-ended clock signal sources are allowed. The unused clock input is internally biased at the logical threshold
(1.65 V for nominal supply conditions), and should be correctly decoupled.
1999 Sep 16
14