TDA8798 Datasheet, PDF (15/24 Pages) NXP Semiconductors – Dual 8-bit, 100 Msps A/D converter with DPGA

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SMODE
SEN
SCLK
tsu(SEN-SCLK)
parallel load mode
th(SMODE-SEN)
th(SMODE-SCLK)
t _W(SCLKH)
t _W(SCLKL)
tsu(SEN-SCLK)
th(SEN-SCLK)
count-up/count-down mode
50%
tsu(SEN-SCLK)
50%
50%
tsu(SDATA-SCLK)
up = 1
down = 0
up = 1
down = 0
SDATA
SI GAIN
CONTROL
REGISTER
D5
D4
D3
D2
D1
D0
(MSB)
(LSB)
td(SEN-Q)
td(SCLK-Q)
D5 D4 D3 D2 D1 D0 REG +/−1 REG +/−1
tst(G-G)
DPGA
OUTPUTS
10%
90%
tPD
MGM865
Fig.4 Timing diagram of serial interface.