TDA8798 Datasheet, PDF (12/24 Pages) NXP Semiconductors – Dual 8-bit, 100 Msps A/D converter with DPGA

Philips Semiconductors
Dual 8-bit, 100 Msps A/D converter with
DPGA
Objective specification
TDA8798
SYMBOL
PARAMETER
CONDITIONS
MIN.
NOISE
V_n(o)(rms)
output referred noise
(RMS value)
DPGA at G_(max);
−
Z_i = 50 Ω; noise
bandwidth = 15 MHz
ADC (without DPGA; f_CLK = 100 MHz; from buffer input to digital output)
ANALOG INPUTS (BUF1, BUF1N, BUF2 AND BUF2N)
V_{i(dif)(FS)(p-p)}
differential input voltage
full-scale amplitude;
(peak-to-peak value)
V_i(cm)(ADC)
I_i(ADC)
R_i(ADC)
C_i(ADC)
common mode input voltage
input current
input resistance
input capacitance
STATIC LINEARITY
at V_i(cm)(ADC)
NL_dc(i)
DC integral non-linearity
ramp input;
without DPGA
NL_dc(dif)
DC differential non-linearity
with DPGA
at G_(min)
ramp input;
without DPGA
DYNAMIC PERFORMANCE
with DPGA
at G_(min)
THD
S/N
total harmonic distortion
signal-to-noise ratio
f_i = 4.43 MHz
without harmonics
BANDWIDTH
B_{(−3dB)(ADC)} ADC −3 dB analog bandwidth
CROSSTALK BETWEEN ADC1 AND ADC2
α_ct
crosstalk between channels
CLOCK INPUTS: CLK1, CLK1N, CLK2 AND CLK2N; note 1
V_IL
LOW-level clock input voltage
V_IH
HIGH-level clock input voltage
I_IH
HIGH-level clock input current
I_IL
LOW-level clock input current
DIGITAL CONTROL INPUTS (OE, TE, TEST, DPGAEN AND SR)
V_IL
LOW-level input voltage
V_IH
HIGH-level input voltage
I_IH
HIGH-level input current
I_IL
LOW-level input current
−
−
−
−
−
−
−
−
−
−
−
−
−
−
2.0
−
−100
−
2.0
−5
−5
TYP.
tbf
500
tbf
tbf
20
3
±1.0
±3.0
±0.5
±0.5
−55
−46
120
−40
−
−
−
−
−
−
−
−
MAX. UNIT
2
mV_rms
−
mV
−
V
−
µA
−
kΩ
−
pF
tbf LSB
tbf LSB
tbf LSB
tbf LSB
−
dB
−
dB
−
MHz
−
dB
0.8 V
V_DDD V
100 µA
−
µA
0.8 V
V_DDD V
+5 µA
+5 µA
1999 Sep 16
12