TDA8358J Datasheet, PDF(7/20 Page) NXP Semiconductors – Full bridge vertical deflection output circuit in LVDMOS with east-west amplifier

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TDA8358J Datasheet, PDF (7/20 Pages) NXP Semiconductors – Full bridge vertical deflection output circuit in LVDMOS with east-west amplifier

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Philips Semiconductors

Full bridge vertical deï¬ection output circuit

in LVDMOS with east-west ampliï¬er

Product speciï¬cation

TDA8358J

CHARACTERISTICS

VP = 12 V; VFB = 45 V; fvert = 50 Hz; VI(bias) = 880 mV; Tamb = 25 Â°C; measured in test circuit of Fig.3; unless otherwise

speciï¬ed.

SYMBOL

PARAMETER

CONDITIONS

MIN. TYP. MAX. UNIT

Supplies

VFB

Iq(P)(av)

Iq(P)

Iq(FB)(av)

operating supply voltage

ï¬yback supply voltage

average quiescent supply current

quiescent supply current

average quiescent ï¬yback supply

current

note 1

during scan

no signal; no load

during scan

7.5 12

2VP 45

Inputs A and B

Vi(dif)(p-p)

differential input voltage

(peak-to-peak value)

note 2

1000 1500 mV

VI(bias)

II(bias)

input bias voltage

input bias current

note 2

100 880 1600 mV

ÂµA

Outputs A and B

Vloss(1)

voltage loss ï¬rst scan part

note 3

Io = 1.1 A

4.5 V

Io = 1.6 A

6.6 V

Vloss(2)

voltage loss second scan part

note 4

Io = â1.1 A

3.3 V

Io = â1.6 A

4.8 V

Io(p-p)

output current (peak-to-peak value)

3.2 A

linearity error

Io(p-p) = 3.2 A; notes 5 and 6

adjacent blocks

non adjacent blocks

Voffset

offset voltage

âVoffset(T) offset voltage variation with

temperature

across RM; Vi(dif) = 0 V

VI(bias) = 200 mV

VI(bias) = 1 V

across RM; Vi(dif) = 0 V

Â±15 mV

Â±20 mV

ÂµV/K

Gv(ol)

fâ3dB(h)

âGv(T)

DC output voltage

open-loop voltage gain

high â3 dB cut-off frequency

voltage gain

voltage gain variation with

temperature

Vi(dif) = 0 V

notes 7 and 8

open-loop

note 9

0.5VP â

kHz

10â4 Kâ1

PSRR

power supply rejection ratio

note 10

1999 Dec 22

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