TDA4856 Datasheet, PDF (7/56 Pages) NXP Semiconductors – I2C-bus autosync deflection controller for PC monitors

Philips Semiconductors
I²C-bus autosync deflection controller for
PC monitors
Product specification
TDA4856
Frequency-locked loop
The frequency-locked loop can lock the horizontal
oscillator over a wide frequency range. This is achieved by
a combined search and PLL operation. The frequency
range is preset by two external resistors and the
recommended maximum ratio is ^f-f-m-_m---^a-_i-_n-^x = ^6---1-.--5-
This can, for instance, be a range from 15.625 to 90 kHz
with all tolerances included.
Without a horizontal sync signal the oscillator will be
free-running at f_min. Any change of sync conditions is
detected by the internal coincidence detector. A deviation
of more than 4% between horizontal sync and oscillator
frequency switches the horizontal section into search
mode. This means that PLL1 control currents are switched
off immediately. The internal frequency detector then
starts tuning the oscillator. Very small DC currents at
HPLL1 (pin 26) are used to perform this tuning with a well
defined change rate. When coincidence between
horizontal sync and oscillator frequency is detected, the
search mode is first replaced by a soft-lock mode which
lasts for the first part of the next vertical period.
The soft-lock mode is then replaced by a normal PLL
operation. This operation ensures smooth tuning and
avoids fast changes of horizontal frequency during
catching.
In this concept it is not allowed to load HPLL1.
The frequency dependent voltage at this pin is fed
internally to HBUF (pin 27) via a sample-and-hold and
buffer stage. The sample-and-hold stage removes all
disturbances caused by horizontal sync or composite
vertical sync from the buffered voltage. An external
resistor connected between pins HBUF and HREF defines
the frequency range.
Out-of-lock indication (pin HUNLOCK)
Pin HUNLOCK is floating during search mode, or if a
protection condition is true. All this can be detected by the
microcontroller if a pull-up resistor is connected to its own
supply voltage.
For an additional fast vertical blanking at grid 1 of the
picture tube a 1 V signal referenced to ground is available
at this output. The continuous protection blanking
(see Section “Video clamping/vertical blanking generator”)
is also available at this pin. Horizontal unlock blanking can
be switched off, by control bit BLKDIS via the I²C-bus
while vertical blanking is maintained.
Horizontal oscillator
The horizontal oscillator is of the relaxation type and
requires a capacitor of 10 nF at HCAP (pin 29).
For optimum jitter performance the value of 10 nF must
not be changed.
The minimum oscillator frequency is determined by a
resistor from HREF to ground. A resistor connected
between pins HREF and HBUF defines the frequency
range.
The reference current at pin HREF also defines the
integration time constant of the vertical sync integration.
Calculation of line frequency range
The oscillator frequencies f_min and f_max must first be
calculated. This is achieved by adding the spread of the
relevant components to the highest and lowest sync
frequencies f_sync(min) and f_sync(max). The oscillator is driven
by the currents in R_HREF and R_HBUF.
The following example is a 31.45 to 90 kHz application:
Table 1 Calculation of total spread
spread of
IC
C_HCAP
R_HREF, R_HBUF
Total
for f_max
±3%
±2%
±2%
±7%
for f_min
±5%
±2%
±2%
±9%
Thus the typical frequency range of the oscillator in this
example is:
f_max = f_sync(max) × 1.07 = 96.3 kHz
f_min = ^f--s---^y-1--ⁿ--.^c-0--⁽--9^m----ⁱ-ⁿ--⁾ = 28.4 kHz
The resistors R_HREF and R_HBUFpar can be calculated using
the following formulae:
R_HREF = _f--m----_i-_n----₊---7--0--8-.--0-^×--0---k-1---H2-----z_×----^×-f--_m2--k-_i--_n^Ω--_[---k---H-----z----_] = 2.61 kΩ
R_HBUFpar = _f--m----_a---_x---₊---7--0--8--.-0--^×--0--k-1---H2-----z_×----^×-f--_m2--k--_a--^Ω_x---_[--k----H-----z---_]- = 726 Ω .
The resistor R_HBUFpar is calculated as the value of R_HREF
and R_HBUF in parallel.
1999 Jul 13
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