TDA4856 Datasheet, PDF (35/56 Pages) NXP Semiconductors – I2C-bus autosync deflection controller for PC monitors

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List of I²C-bus controlled functions
I²C-bus data can be transmitted in direct or buffered mode and is defined by the MSB of the register subaddress:
• SAD1 is the register subaddress to be used for transmissions in direct mode
• SAD2 is the register subaddress to be used for transmissions in buffered mode.
Table 6 Controlled functions; notes 1 and 2
FUNCTION
Horizontal size
Horizontal
position
Horizontal
pincushion
NAME
HSIZE
HPOS
HPIN
BITS
SAD1
(HEX)
SAD2
(HEX)
D7
REGISTER ASSIGNMENT
D6 D5 D4 D3 D2 D1
D0
CONTROL
BIT
RANGE
8 01 81 D7 D6 D5 D4 D3 D2 D1 D0
−
0.1 to 3.6 V
8 07 87 D7 D6 D5 D4 D3 D2 D1 D0
−
±13% of horizontal
period
6 0F 8F X # D5 D4 D3 D2 D1 D0
−
0 to 1.42 V
Horizontal
trapezium
correction
HTRAP 6 03 83 X X D5 D4 D3 D2 D1 D0
−
±500 mV (p-p)
Horizontal
HCORT 6 04 84 X # D5 D4 D3 D2 D1 D0 VSC +15 to −46% of
corner correction
parabola amplitude
at top of picture
Horizontal
HCORB 6 02 82 X # D5 D4 D3 D2 D1 D0 VSC +15 to −46% of
corner correction
parabola amplitude
at bottom of
picture
Horizontal
HPARAL 6 09 89 # # D5 D4 D3 D2 D1 D0 ACD ±1.2% of horizontal
parallelogram
period
EW pin balance HPINBAL 6 0B 8B # # D5 D4 D3 D2 D1 D0 ACD ±1.2% of horizontal
period
Vertical size
VSIZE 7 08 88 # D6 D5 D4 D3 D2 D1 D0
−
60 to 100%
Vertical position VPOS 7 0D 8D X D6 D5 D4 D3 D2 D1 D0
−
±11.5%
Vertical gain
VGAIN 6 0A 8A X # D5 D4 D3 D2 D1 D0
−
70 to 100%
Vertical offset
VOFFS 4 0E 8E # # # # D3 D2 D1 D0
−
±4%
Vertical linearity VLIN
4 05 85 D7 D6 D5 D4 # # # #
VSC −2 to −46%
Vertical linearity VLINBAL 4 05 85 # # # # D3 D2 D1 D0
−
±1.4% of 100%
balance
vertical size
FUNCTION
TRACKS WITH
−
−
VSIZE, VOVSCN,
VPOS, HSIZE and
HSMOD
VSIZE, VOVSCN,
VPOS, HSIZE and
HSMOD
VSIZE, VOVSCN,
VPOS, HSIZE and
HSMOD
VSIZE, VOVSCN,
VPOS, HSIZE and
HSMOD
VSIZE, VOVSCN
and VPOS
VSIZE, VOVSCN
and VPOS
VSMOD
VSMOD
−
−
VSIZE, VOVSCN,
VPOS and VSMOD
VSIZE, VOVSCN,
VPOS and VSMOD