TDA4856 Datasheet, PDF (4/56 Pages) NXP Semiconductors – I2C-bus autosync deflection controller for PC monitors

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VSYNC 14
(TTL level)
VERTICAL
SYNC INPUT
AND POLARITY
CORRECTION
clamping
blanking
CLBL 16
VIDEO CLAMPING
AND
VERTICAL BLANK
HUNLOCK ₁₇
HUNLOCK
OUTPUT
9.2 to 16 V
SDA 19
SCL 18
I²C-BUS
RECEIVER
VCC ₁₀
PGND 7
SGND 25
SUPPLY
AND
REFERENCE
VERTICAL
SYNC
INTEGRATOR
22
kΩ
(1%)
VREF
23
100
nF
(5%)
EHT compensation
via vertical size
EHT compensation
150
via horizontal size
nF
VCAP VAGC
24
22
VSMOD
21
HSMOD
31
EWDRV
11
7V
1.2 V
VERTICAL
OSCILLATOR
AND AGC
VERTICAL POSITION
VERTICAL SIZE AND
VERTICAL OVERSCAN
PROTECTION
AND SOFT START
I²C-BUS REGISTERS
COINCIDENCE DETECTOR
FREQUENCY DETECTOR
EHT COMPENSATION
HORIZONTAL AND
VERTICAL SIZE
EW OUTPUT
HORIZONTAL PINCUSHION
HORIZONTAL CORNER
HORIZONTAL TRAPEZIUM
HORIZONTAL SIZE
VERTICAL OUTPUT
VERTICAL LINEARITY
VERTICAL LINEARITY
BALANCE
12 VOUT2
13 VOUT1
TDA4856
X-RAY
PROTECTION
ASYMMETRIC
EW-CORRECTION
OUTPUT
20 ASCOR
FOCUS
HORIZONTAL
AND VERTICAL
32 FOCUS
B+
CONTROL
6 BDRV
4 BSENS
3 BOP
5 BIN
or
B+ CONTROL(2)
APPLICATION
HSYNC 15
(TTL level)
H/C SYNC INPUT
AND POLARITY
CORRECTION
(video)
PLL1 AND
HORIZONTAL
POSITION
HORIZONTAL
OSCILLATOR
3.3 kΩ
100 nF
26
27
HPLL1 HBUF
28
HREF
8.2
RHBUF ₍₁₎
nF
RHREF
(1%)
29
HCAP
10 nF
(2%)
PLL2, PARALLELOGRAM,
PIN UNBALANCE AND
SOFT START
30
HPLL2
12 nF
1
HFLB
HORIZONTAL
OUTPUT
8 HDRV
9
2
XSEL XRAY
MGS272
(1) For the calculation of f_H range see Section “Calculation of line frequency range”.
(2) See Figs 22 and 23.
Fig.1 Block diagram and application circuit.