SAA8112HL Datasheet, PDF (7/40 Pages) NXP Semiconductors – Digital camera signal processor and microcontroller

Philips Semiconductors
Digital camera signal processor and
microcontroller
Product specification
SAA8112HL
SYMBOL
P0.5
P0.4
P0.3
P0.2
P0.1
P0.0
V_DD5
GND5
PSEN
ALE
P3.7/RD
P3.6/WR
P3.5/T1
P3.4/T0
P3.3/INT1
P3.2/INT0
P3.1/TXD
P3.0/RXD
P4.7
P4.6
P4.5
P4.4
P4.3
P4.2
P4.1
P4.0
DGND4
V_DDD4
UCCLK
UCM
UCRST
SNCL
SNDA
SNRES
PXQ
VS
HREF
V_DD1
LLC
GND1
YUV7
2000 Jan 18
PIN I/O
DESCRIPTION
41 I/O Port 0 bidirectional; bit 5
42 I/O Port 0 bidirectional; bit 4
43 I/O Port 0 bidirectional; bit 3
44 I/O Port 0 bidirectional; bit 2
45 I/O Port 0 bidirectional; bit 1
46 I/O Port 0 bidirectional; bit 0
47 P supply voltage 5 for output buffers
48 P ground 5 for output buffers
49 O program store enable output for external memory (active LOW)
50 O address latch enable output for external latch
51 O Port 3 output; bit 7/external data memory read output (active LOW)
52 O Port 3 output; bit 6/external data memory write output (active LOW)
53 I Port 3 input; bit 5/Timer 1 external input
54 I Port 3 input; bit 4/Timer 0 external input
55 I Port 3 input; bit 3/external interrupt 1
56 I Port 3 input; bit 2/external interrupt 0
57 I/O Port 3 input; bit 1/serial output port (UART)
58 I/O Port 3 input; bit 0/serial input port (UART)
59 I/O Port 4 bidirectional; bit 7
60 I/O Port 4 bidirectional; bit 6
61 I/O Port 4 bidirectional; bit 5
62 I/O Port 4 bidirectional; bit 4
63 I/O Port 4 bidirectional; bit 3
64 I/O Port 4 bidirectional; bit 2
65 I/O Port 4 bidirectional; bit 1
66 I/O Port 4 bidirectional; bit 0
67 P digital ground 4 for input buffers and predrivers and to the digital core
68 P digital voltage 4 for input buffers and predrivers and to the digital core
69 I clock for internal 80C51
70 I (test) mode control signal for internal 80C51
71 I Power-on reset for internal 80C51
72 I clock for DSP-SNERT interface (UART mode 0)
73 I/O data I/O for DSP-SNERT interface (UART mode 0)
74 I reset for DSP-SNERT interface (UART mode 0)
75 O pixel qualifier output for YUV-port
76 O vertical synchronization output for YUV-port
77 O horizontal reference output for YUV-port
78 P supply voltage 1 for output buffers
79 O line-locked clock (delayed CLK2) for YUV-port
80 P ground 1 for output buffers
81 O multiplexed YUV; bit 7
7