SAA8112HL Datasheet, PDF (17/40 Pages) NXP Semiconductors – Digital camera signal processor and microcontroller

Philips Semiconductors
Digital camera signal processor and
microcontroller
Product specification
SAA8112HL
8.9 Microcontroller
The embedded microcontroller is basically a 80C654 core
(80C51 family) with five ports. Its functionality is standard,
except that the ports are dedicated inputs, outputs or I/O
ports (see Chapter 7). Ports P0 and P2 are available for
connection to an emulator or to an external program
PROM.
The microcontroller can control the AE and the AWB loops
and can download the settings for the DSP registers from
an optional EEPROM at power-up or reset, for instance.
The microcontroller includes the following features:
• 32 kbyte internal ROM
• 512 byte RAM
• Hardware I²C-bus interface: P1.7 and P1.6
• Hardware UART interface: P3.0 and P3.1
• Power-down mode
• Two timers
• P4 is an open-drain port
• P0, P1, P2 and P3 are pull-up ports.
Table 3 80C51 Special Function Registers
SFR
NAME
DESCRIPTION
B
B register
ACC accumulator
SIADR serial interface address
SIDAT serial interface data
SISTA serial interface status
SICON serial interface control
PSW program status word
P4
Port 4
IP
interrupt priority
P3
Port 3
IE
interrupt enable
P2
Port 2
SBUF serial data buffer
SCON serial controller
P1
Port 1
TH1 timer high 1
TH0 timer high 0
TL1 timer low 1
TL0 timer low 0
TMOD timer mode
TCON timer control
PCON power control
DPH data pointer high
DPLl data pointer low
SP
stack pointer
P0
Port 0
SFR
ADD
F0H
E0H
DBH
DAH
D9H
D8H
D0H
C0H
B8H
B0H
A8H
A0H
99H
98H
90H
8DH
8CH
8BH
8AH
89H
88H
87H
83H
82H
81H
80H
DATA
BIT 7
B7
ACC7
SA6
SD7
ST7
CR2
CY
P4.7
−
RD
EA
AD15
−
SM0
SDA
−
−
−
−
GATE
TF1
−
−
−
SP7
AD7
DATA
BIT 6
B6
ACC6
SA5
SD6
ST6
ENS1
AC
P4.6
IP6
WR
IE6
AD14
−
SM1
SCL
−
−
−
−
C/T
TR1
−
−
−
SP6
AD6
DATA
BIT 5
B5
ACC5
SA4
SD5
ST5
STA
F0
P4.5
IP5
T1
IE5
AD13
−
SM2
P1.5
−
−
−
−
M1
TF0
−
−
−
SP5
AD5
DATA
BIT 4
B4
ACC4
SA3
SD4
ST4
STO
RS1
P4.4
IP4
T0
IE4
AD12
−
REN
P1.4
−
−
−
−
M0
TR0
−
−
−
SP4
AD4
DATA
BIT 3
B3
ACC3
SA2
SD3
ST3
SI
RS0
P4.3
PT1
INT1
ET1
AD11
−
TB8
P1.3
−
−
−
−
GATE
IE1
−
−
−
SP3
AD3
DATA
BIT 2
B2
ACC2
SA1
SD2
0
AA
OV
P4.2
PX1
INT0
EX1
AD10
−
RB8
P1.2
−
−
−
−
C/T
IT1
−
−
−
SP2
AD2
DATA
BIT 1
B1
ACC1
SA0
SD1
0
CR1
−
P4.1
PT0
TXD
ET0
AD9
−
T1
P1.1
−
−
−
−
M1
IE0
PD
−
−
SP1
AD1
DATA
BIT 0
B0
ACC0
GC
SD0
0
CR0
P
P4.0
PX0
RXD
EX0
AD8
−
R1
P1.0
−
−
−
−
M0
IT0
IDL
−
−
SP0
AD0
2000 Jan 18
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