SAA8112HL Datasheet, PDF (25/40 Pages) NXP Semiconductors – Digital camera signal processor and microcontroller

Philips Semiconductors
Digital camera signal processor and
microcontroller
Product specification
SAA8112HL
Table 15 Register OUTF_AVSC (address: 0x50H)
X = don’t care.
BIT
PARAMETER
76543210
DESCRIPTION
AVSYNC (HREF) period (in CLK1 cycles during active video)
1 1 1 1 2560 CLK1 cycles when AVVALID (PXQ) is high
1 1 1 0 1920 CLK1 cycles
1 1 0 1 1280 CLK1 cycles
1 1 0 0 960 CLK1 cycles
1 0 1 1 640 CLK1 cycles
1 0 1 0 480 CLK1 cycles
1 0 0 1 320 CLK1 cycles
1 0 0 0 240 CLK1 cycles
0 1 1 1 160 CLK1 cycles
0 1 1 0 120 CLK1 cycles
0 1 0 1 80 CLK1 cycles
0 1 0 0 60 CLK1 cycles
0 0 1 1 40 CLK1 cycles
0 0 1 0 30 CLK1 cycles
0 0 0 1 20 CLK1 cycles
0 0 0 0 15 CLK1 cycles
output format select code
111
IEEE-1394 4 : 4 : 4 mode (IEEE-1384 camera mode_0)
110
IEEE-1394 4 : 2 : 2 mode (IEEE-1384 camera mode_1 and mode_3)
101
IEEE-1394 4 : 1 : 1 mode (IEEE-1384 camera mode_2)
100
IEEE-1394 4 : 0 : 0 (B and W) mode (IEEE-1384 camera mode_5)
0XX
standard 4 : 2 : 2 mode
X
MSB of SY (VS) duration
2000 Jan 18
25