PHN205 Datasheet, PDF (7/12 Pages) NXP Semiconductors – Dual N-channel enhancement mode MOS transistor

Philips Semiconductors
Dual N-channel enhancement mode
MOS transistor
Product specification
PHN205
1250
handbook, halfpage
C
(pF)
1000
MGG343
750
(1)
500
(2)
250
(3)
0
0
4
8
12
16
20
VDS (V)
V_GS = 0; f = 1 MHz; T_j = 25 °C.
(1) C_iss.
(2) C_oss.
(3) C_rss.
Fig.6 Capacitance as a function of drain-source
voltage; typical values.
handbook,³h⁰alfpage
ID
(1)
(A)
20
10
0
0
4
MGG344
(2)
(3)
(4)
(5)
(6)
8 _{VDS (V)} 12
T_amb = 25 °C; t_p = 80 µs; δ = 0.
(1) V_GS = 10 V.
(2) V_GS = 5 V.
(3) V_GS = 4.5 V.
(4) V_GS = 4 V.
(5) V_GS = 3.5 V.
(6) V_GS = 3 V.
Fig.7 Output characteristics; typical values.
30
handbook, halfpage
ID
(A)
20
10
MGG345
handbook,¹h⁶alfpage
V
(V)
12
8
(1)
4
MGG346
(2)
0
0
2
4 _{VGS (V)} 6
V_DS = 10 V; T_amb = 25 °C; t_p = 80 µs; δ = 0.
Fig.8 Transfer characteristics; typical values.
1997 Oct 22
0
0
4
8
12
16
QG (nC)
V_DD = 12.5 V; I_D = 3.2 A; T_amb = 25 °C.
(1) V_DS.
(2) V_GS.
Fig.9 Gate-source voltage and drain-source
voltage as a function of total gate charge;
typical values.
7