PHN205 Datasheet, PDF (2/12 Pages) NXP Semiconductors – Dual N-channel enhancement mode MOS transistor

Philips Semiconductors
Dual N-channel enhancement mode
MOS transistor
Product specification
PHN205
FEATURES
• High-speed switching
• No secondary breakdown
• Very low on-state resistance.
APPLICATIONS
• Motor and actuator driver
• Power management
• Synchronized rectification.
DESCRIPTION
Two N-channel enhancement mode MOS transistors in an
8-pin plastic SOT96-1 (SO8) package.
CAUTION
The device is supplied in an antistatic package.
The gate-source input must be protected against static
discharge during transport or handling.
PINNING - SOT96-1 (SO8)
PIN
SYMBOL
1
s₁
2
g₁
3
s₂
4
g₂
5
d₂
6
d₂
7
d₁
8
d₁
DESCRIPTION
source 1
gate 1
source 2
gate 2
drain 2
drain 2
drain 1
drain 1
handbook, halfpage
8
5
d1 d1
d2 d2
1
4
MAM117
s1
g1
s2
g2
Fig.1 Simplified outline and symbol.
QUICK REFERENCE DATA
SYMBOL
PARAMETER
Per N-channel
V_DS
V_SD
V_GS
V_GSth
I_D
R_DSon
P_tot
drain-source voltage (DC)
source-drain diode forward voltage
gate-source voltage (DC)
gate-source threshold voltage
drain current (DC)
drain-source on-state resistance
total power dissipation
CONDITIONS
MIN.
MAX.
UNIT
−
I_S = 1.25 A
−
−
I_D = 1 mA; V_DS = V_GS 1
T_s = 80 °C
−
I_D = 3.2 A; V_GS = 10 V −
T_s = 80 °C
−
30
V
1
V
±20
V
2.8
V
6.4
A
50
mΩ
3.5
W
1997 Oct 22
2