PHN205 Datasheet, PDF (3/12 Pages) NXP Semiconductors – Dual N-channel enhancement mode MOS transistor

Philips Semiconductors
Dual N-channel enhancement mode
MOS transistor
Product specification
PHN205
LIMITING VALUES
In accordance with the Absolute Maximum Rating System (IEC 134).
SYMBOL
PARAMETER
CONDITIONS
MIN. MAX. UNIT
Per N-channel
V_DS
drain-source voltage (DC)
V_GS
gate-source voltage (DC)
I_D
drain current (DC)
I_DM
peak drain current
P_tot
total power dissipation
T_stg
storage temperature
T_j
operating junction temperature
Source-drain diode
I_S
source current (DC)
I_SM
peak pulsed source current
T_s = 80 °C; note 1
note 2
T_s = 80 °C; note 3
T_amb = 25 °C; note 4
T_amb = 25 °C; note 5
T_amb = 25 °C; note 6
T_s = 80 °C
note 2
−
30
V
−
±20
V
−
6.4
A
−
25
A
−
3.5
W
−
2.6
W
−
1.1
W
−
1.5
W
−65
+150 °C
−65
+150 °C
−
3.5
A
−
14
A
Notes
1. T_s is the temperature at the soldering point of the drain lead.
2. Pulse width and duty cycle limited by maximum junction temperature.
3. Maximum permissible dissipation per MOS transistor. Both devices may be loaded up to 3.5 W at the same time.
4. Maximum permissible dissipation per MOS transistor. Device mounted on printed-circuit board with an R_{th a-tp}
(ambient to tie-point) of 27.5 K/W.
5. Maximum permissible dissipation per MOS transistor. Device mounted on printed-circuit board with an R_{th a-tp}
(ambient to tie-point) of 90 K/W.
6. Maximum permissible dissipation if only one MOS transistor dissipates. Device mounted on printed-circuit board with
an R_{th a-tp} (ambient to tie-point) of 90 K/W.
THERMAL CHARACTERISTICS
SYMBOL
PARAMETER
R_{th j-s}
thermal resistance from junction to soldering point
VALUE
20
UNIT
K/W
1997 Oct 22
3