BUK109-50GL Datasheet, PDF (7/11 Pages) NXP Semiconductors – PowerMOS transistor Logic level TOPFET

Philips Semiconductors
PowerMOS transistor
Logic level TOPFET
Product specification
BUK109-50GL
Energy & Time
1
BUK109-50GL
Time / ms
0.5
Energy / J
Tj(TO)
0
-60 -20
20
60 100 140 180 220
Tmb / C
Fig.14. Typical overload protection characteristics.
Conditions: V_DD = 13 V; V_IS = 5 V; SC load = 30 mΩ
ID / A
30
BUK109-50GL
20
typ.
10
0
50
60
70
VIS / V
Fig.15. Typical clamping characteristics, 25 ˚C.
I_D = f(V_DS); conditions: V_IS = 0 V; t_p ≤ 50 µs
VIS(TO) / V
2
1
max.
typ.
min.
II / uA
500
BUK109-50GL
400
Tj = 25 C
300
200
150 C
100
0
0
2
4
6
8
10
VIS / V
Fig.17. Typical DC input characteristics.
I_I = f(V_IS); normal operation; parameter: T_j
IISL / mA
3
2
PROTECTION LATCHED
BUK109-50GL
RESET
1
NORMAL
0
0
2
4
6
8
VIS / V
Fig.18. Typical DC input characteristics, T_j = 25 ˚C.
I_ISL = f(V_IS); overload protection operated ⇒ I_D = 0 A
IS / A
100
BUK109-50GL
50
0
-60 -40 -20 0 20 40 60 80 100 120 140
Tj / C
Fig.16. Input threshold voltage.
V_IS(TO) = f(T_j); conditions: I_D = 1 mA; V_DS = 5 V
0
0
Fig.19.
1
2
VSD / V
Typical reverse diode current, T_j = 25 ˚C.
I_S = f(V_SDS); conditions: V_IS = 0 V
June 1996
7
Rev 1.000