UJA1061 Datasheet, PDF (6/81 Pages) NXP Semiconductors – Low speed CAN/LIN system basis chip

Philips Semiconductors
Low speed CAN/LIN system basis chip
Objective specification
UJA1061
5 PINNING
SYMBOL
n.c.
n.c.
TXDL
V1
RXDL
RSTN
INTN
EN
SDI
SDO
SCK
SCS
TXDC
RXDC
n.c.
TEST
INH/LIMP
WAKE
RTL
V2
CANH
CANL
GND
RTH
LIN
RTLIN
BAT14
n.c.
2004 Mar 22
PIN
DESCRIPTION
1
not connected
2
not connected
3
transmit data input to activate the LIN output drive; LOW = LIN-bus dominant;
HIGH = LIN-bus recessive
4
regulated supply voltage output for microcontroller; voltage is 5 V, 3.3 V, 3 V
or 2.5 V according to version
5
receive data output for reading data from the LIN-bus; LOW when LIN-bus is
dominant; HIGH when LIN-bus is recessive
6
active LOW push-pull output used to reset the microcontroller; the UJA1061 also
monitors the voltage on pin RSTN for any clamping situation (fail-safe)
7
active LOW open-drain output used to interrupt the microcontroller; pin INTN is to
be wire-ANDed with other interrupt outputs within the ECU
8
push-pull enable output related to voltage regulator V1; active HIGH if the watchdog
is triggered successfully and a control bit is set; immediately pulled LOW with any
reset event (e.g. a watchdog overflow); full set/clear application access via SPI
while watchdog is served properly
9
SPI data input
10
SPI data output
11
SPI clock input
12
active LOW select input used to enable an SPI access
13
transmit data input that activates the CAN output driver; LOW = CAN-bus dominant;
HIGH = CAN-bus recessive
14
receive data output for reading data from the CAN-bus; LOW when CAN-bus is
dominant; HIGH when CAN-bus is recessive; output is continuously LOW upon a
wake-up event received via the CAN-bus
15
not connected
16
test pin; connect to ground in application
17
14 V battery related inhibit output for system extension, or ‘limp home’ output,
activated in Fail-safe mode (default floating)
18
42 V battery related local wake-up input
19
CAN termination resistor connection; in case of a CANL bus wire error this line is
terminated with a selectable impedance
20
regulated 5 V supply output reserved for CAN transceiver; an external buffer
capacitor connects to this pin
21
CAN-bus line; HIGH in dominant state and LOW in recessive state
22
CAN-bus line; LOW in dominant state and HIGH in recessive state
23
ground
24
CAN termination resistor connection; in case of a CANH bus wire error this line is
terminated with a selectable impedance
25
LIN-bus line; LOW when LIN-bus is dominant, HIGH when LIN-bus is recessive
26
LIN-bus termination resistor connection
27
14 V battery supply input
28
not connected
6