UJA1061 Datasheet, PDF (40/81 Pages) NXP Semiconductors – Low speed CAN/LIN system basis chip

Philips Semiconductors
Low speed CAN/LIN system basis chip
Objective specification
UJA1061
BIT SYMBOL DESCRIPTION
VALUE
FUNCTION
1
CANIE CAN Interrupt Enable
1
CAN-bus event results in a wake-up interrupt
0
CAN-bus event results in a reset
0
LINIE LIN Interrupt Enable
1
LIN-bus event results in a wake-up interrupt
0
LIN-bus event results in a reset
Notes
1. This flag is cleared automatically upon each overflow event. It has to be set in software each time the interrupt
behaviour is required (fail-safe behaviour).
2. If V2 or V3 is shut down due to a short-circuit, or activation of V2 or V3 fails due to a short-circuit, the interrupt is
forced. V2 can be activated again by clearing CTC (CAN Transmitter Control), setting CAN mode or via a wake-up
event on CAN. V3 can be activated setting bit V3C to a value other than ‘00’.
2004 Mar 22
40