UJA1061 Datasheet, PDF (29/81 Pages) NXP Semiconductors – Low speed CAN/LIN system basis chip

Philips Semiconductors
Low speed CAN/LIN system basis chip
Objective specification
UJA1061
t_on(CS) = 16 or 32 ms
t_w(CS) = 384 µs
V₃
sample
active
t_su(CS) = 256 µs ^{approx. 70 %}
V_WAKE
signal already HIGH
due to biasing (history)
flip flop
button pushed button released
signal remains LOW
due to biasing (history)
V_INTM
Fig.12 Pin WAKE, cyclic sampling via V3.
mce633
6.11 Interrupt output
In order to support multiple interrupt sources within a
system, pin INTN provides an open-drain output
configuration.
Whenever at least one bit is set within the interrupt register
this pin is forced LOW. Reading the interrupt register
clears all set bits. Only these bits are cleared as they have
definitely been read during that access.
The interrupt register will be cleared also during a system
reset (RSTN LOW).
6.12 Temperature protection
The temperature of the UJA1061 chip is monitored as long
as the microcontroller voltage regulator V1 is active.
To avoid any unexpected shut-down of the application by
the UJA1061, the temperature protection will not switch off
any part of the UJA1061 or activate a defined system stop
of its own accord. A too-high temperature only generates
an interrupt to the microcontroller, if enabled, and the
corresponding status bit is set. The microcontroller can
now decide whether to switch off parts of the UJA1061 in
order to decrease the chip temperature.
6.13 SPI interface
The Serial Peripheral Interface (SPI) provides the
communication link with the microcontroller and supports
multi-slave and multi-master operation. The SPI is
configured for full duplex data transfer; while new control
data is shifted-in, status information is automatically
returned. All registers provide a read-only access option.
Thus all status bits can be read back by the application at
any time.
The SPI interface with a data rate up to 2 Mbit/s provides
four interface signals, including chip select (see Fig.13).
Any bit-sampling is performed with the falling clock edge
and the data is shifted with the rising clock edge.
All SPI interface signals are derived from V1 in order to
avoid problems with reversed supplies.
Most of the registers are only accessible (read and/or
write) during Normal mode or Standby mode. Some other
registers, needed for watchdog initialization and entering
special modes, are only accessible during the Start-up
and/or Restart mode.
2004 Mar 22
29